Self-aligned transistor structures enabling ultra-short channel lengths

Patent metadata

Field	Value
Publication number	US-10546927-B2
Application number	US-201515774064-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Dec 7, 2015
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.

First claim

What is claimed is:

1. An integrated circuit including at least one transistor, the integrated circuit comprising:
a first layer including gallium and nitrogen;
a gate structure at least above the first layer;
a second layer above the first layer and adjacent to opposite sides of the gate structure, the second layer including nitrogen and at least one of aluminum, gallium, or indium; and
a source region and a drain region adjacent to the first layer;
wherein the gate structure has a length between portions of the second layer of less than 100 nanometers.

2. The integrated circuit of claim 1 , wherein the first layer further includes indium.

3. The integrated circuit of claim 1 , wherein the at least one of aluminum, gallium, or indium included in the second layer includes aluminum.

4. The integrated circuit of claim 1 , further comprising spacer structures adjacent to opposite sides of the gate structure, the spacer structures on the second layer, the spacer structures including one or more dielectrics.

5. The integrated circuit of claim 1 , wherein the length between portions of the second layer is less than 20 nanometers.

6. The integrated circuit of claim 1 , wherein the source and drain regions include indium and nitrogen.

7. The integrated circuit of claim 1 , wherein the source and drain regions include n-type dopant.

8. The integrated circuit of claim 1 , wherein the gate structure is adjacent three sides of the first layer.

9. The integrated circuit of claim 1 , wherein the gate structure is around a portion of the first layer.

10. The integrated circuit of claim 1 , further comprising a complementary metal-oxide-semiconductor (CMOS) circuit including the at least one transistor.

11. A computing system comprising the integrated circuit of claim 1 .

12. The integrated circuit of claim 1 , wherein the gate structure includes a gate electrode and a gate dielectric, the gate electrode including one or more metals, the gate dielectric between the gate electrode and the first layer.

13. The integrated circuit of claim 12 , wherein the second layer is absent between the gate dielectric and the first layer.

14. The integrated circuit of claim 1 , further comprising a third layer between the first and second layers, the third layer including nitrogen and at least one of aluminum, gallium, or indium.

15. The integrated circuit of claim 14 , wherein the at least one of aluminum, gallium, or indium included in the third layer is aluminum.

16. An integrated circuit including at least one transistor, the integrated circuit comprising:
a first layer including gallium and nitrogen;
a gate structure at least above the first layer, the gate structure including a gate electrode and a gate dielectric, the gate electrode including one or more metals, the gate dielectric between the gate electrode and the first layer;
spacer structures adjacent to opposite sides of the gate structure, the spacer structures including one or more dielectrics; and
a second layer between the spacer structures and the first layer, the second layer including nitrogen and at least one of aluminum, gallium, or indium;
wherein the gate structure includes a length of less than 100 nanometers between the spacer structures.

17. The integrated circuit of claim 16 , further comprising a bulk silicon substrate, wherein the first layer is between the gate structure and the substrate.

18. The integrated circuit of claim 16 , wherein the first layer further includes indium.

19. The integrated circuit of claim 16 , further comprising a third layer between the first and second layers, the third layer including aluminum and nitrogen.

20. The integrated circuit of claim 16 , wherein the length is less than 20 nanometers between the spacer structures.

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Gardner Sanaz K
• Sung Seung Hoon

Classifications

• H01L29/267

  Electricity · mapped topic

• H01L29/66431

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title