Array substrate and manufacturing method thereof, display panel and display device

US10546882B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10546882-B2
Application numberUS-201715535391-A
CountryUS
Kind codeB2
Filing dateJan 5, 2017
Priority dateApr 29, 2016
Publication dateJan 28, 2020
Grant dateJan 28, 2020

How to read this patent

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides an array substrate, a display panel comprising the array substrate, and a display device, as well as a manufacturing method of the array substrate. The array substrate comprises a base substrate, a metal layer arranged over the base substrate, a conductive material layer arranged on the metal layer, and a connection hole arranged over the conductive material layer to expose the conductive material layer.

First claim

Opening claim text (preview).

The invention claimed is: 1. An array substrate comprising a base substrate; a metal layer arranged over the base substrate; a protective conductive material monolayer arranged on the metal layer; and a connection hole arranged over the protective conductive material monolayer to expose the protective conductive material monolayer, wherein the metal layer comprises a data line, and the protective conductive material monolayer is in a same layer as a pixel electrode layer of the array substrate. 2. The array substrate according to claim 1 , wherein the conductive material monolayer is in a same layer as a display driving electrode layer of the array substrate. 3. The array substrate according to claim 1 , wherein the array substrate comprises a thin film transistor, and the metal layer comprises at least one of a source and a drain of the thin film transistor. 4. The array substrate according to claim 1 , wherein the array substrate further comprises a gate insulating layer arranged between the data line and the base substrate and a passivation layer arranged over the protective conductive material monolayer, the connection hole being arranged in the passivation layer. 5. The array substrate according to claim 1 , wherein the array substrate further comprises a gate insulating layer and a passivation layer arranged successively over the conductive material monolayer, the connection hole being arranged in the gate insulating layer and the passivation layer. 6. The array substrate according to claim 1 , wherein the conductive material monolayer is made of a conductive oxide wherein the conductive oxide includes one or more of an indium tin oxide, an aluminum-doped zinc oxide, an indium-doped zinc oxide and an indium-doped cadmium oxide. 7. A display panel comprising the array substrate according to claim 1 .

Assignees

Inventors

Classifications

  • Electricity · mapped topic

  • Electricity · mapped topic

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

  • comprising manufacture, treatment or coating of substrates · CPC title

  • adapted for preventing breakage, peeling or short circuiting · CPC title

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Frequently asked questions

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What does patent US10546882B2 cover?
The present disclosure provides an array substrate, a display panel comprising the array substrate, and a display device, as well as a manufacturing method of the array substrate. The array substrate comprises a base substrate, a metal layer arranged over the base substrate, a conductive material layer arranged on the metal layer, and a connection hole arranged over the conductive material laye…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/1244. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 28 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).