Thin film transistor and fabrication method thereof, array substrate and display panel
US-2017040343-A1 · Feb 9, 2017 · US
US10546882B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10546882-B2 |
| Application number | US-201715535391-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 5, 2017 |
| Priority date | Apr 29, 2016 |
| Publication date | Jan 28, 2020 |
| Grant date | Jan 28, 2020 |
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The present disclosure provides an array substrate, a display panel comprising the array substrate, and a display device, as well as a manufacturing method of the array substrate. The array substrate comprises a base substrate, a metal layer arranged over the base substrate, a conductive material layer arranged on the metal layer, and a connection hole arranged over the conductive material layer to expose the conductive material layer.
Opening claim text (preview).
The invention claimed is: 1. An array substrate comprising a base substrate; a metal layer arranged over the base substrate; a protective conductive material monolayer arranged on the metal layer; and a connection hole arranged over the protective conductive material monolayer to expose the protective conductive material monolayer, wherein the metal layer comprises a data line, and the protective conductive material monolayer is in a same layer as a pixel electrode layer of the array substrate. 2. The array substrate according to claim 1 , wherein the conductive material monolayer is in a same layer as a display driving electrode layer of the array substrate. 3. The array substrate according to claim 1 , wherein the array substrate comprises a thin film transistor, and the metal layer comprises at least one of a source and a drain of the thin film transistor. 4. The array substrate according to claim 1 , wherein the array substrate further comprises a gate insulating layer arranged between the data line and the base substrate and a passivation layer arranged over the protective conductive material monolayer, the connection hole being arranged in the passivation layer. 5. The array substrate according to claim 1 , wherein the array substrate further comprises a gate insulating layer and a passivation layer arranged successively over the conductive material monolayer, the connection hole being arranged in the gate insulating layer and the passivation layer. 6. The array substrate according to claim 1 , wherein the conductive material monolayer is made of a conductive oxide wherein the conductive oxide includes one or more of an indium tin oxide, an aluminum-doped zinc oxide, an indium-doped zinc oxide and an indium-doped cadmium oxide. 7. A display panel comprising the array substrate according to claim 1 .
Electricity · mapped topic
Electricity · mapped topic
Interconnections, e.g. scanning lines · CPC title
comprising manufacture, treatment or coating of substrates · CPC title
adapted for preventing breakage, peeling or short circuiting · CPC title
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