System and method for substrate wafer back side and edge cross section seals

Patent metadata

Field	Value
Publication number	US-10546750-B2
Application number	US-201614988639-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Sep 3, 2009
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

First claim

What is claimed is:

1. A method of growing epitaxial silicon on a silicon wafer, said method comprising:
depositing a layer of silicon oxide on all entire surfaces and edges of said silicon wafer;
removing said silicon oxide from a front surface of said silicon wafer;
depositing a layer of poly silicon only on a back surface of said silicon wafer, over said silicon oxide;
growing a layer of epitaxial silicon on said front surface of said silicon wafer;
depositing another layer of silicon oxide on all exposed surfaces and edges of said layer of epitaxial silicon and said silicon wafer;
removing said another layer of silicon oxide from a front surface of said layer of epitaxial silicon;
depositing another layer of poly silicon on the back surface of said silicon wafer, over said another layer of silicon oxide; and
growing another layer of epitaxial silicon on said layer of epitaxial silicon.

2. The method of claim 1 wherein said depositing a layer of silicon oxide is configured to reduce auto doping during said growing.

3. The method of claim 1 further comprising doping a region of said layer of epitaxial silicon prior to said growing another layer of epitaxial silicon.

4. The method of claim 1 wherein said another layer of epitaxial silicon comprises a gap characterized by an absence of epitaxial silicon.

5. The method of claim 1 wherein no epitaxial silicon is in contact with silicon of a back side of said wafer.

Assignees

• Vishay Siliconix

Inventors

• Lu Hamilton
• Chau The-Tu
• Terrill Kyle
• Pattanayak Deva N
• Shi Sharon
• Chen Kuo-In
• Xu Robert

Classifications

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3448

  Delta-doping · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P32/15 Primary

  from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping · CPC title