Memory card expansion

US10545901B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10545901-B2
Application numberUS-201515543207-A
CountryUS
Kind codeB2
Filing dateJan 29, 2015
Priority dateJan 29, 2015
Publication dateJan 28, 2020
Grant dateJan 28, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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An apparatus includes a memory card that includes at least one memory module and an expansion connector to connect with at least one expansion memory card. A lane distributor on the memory card interfaces with a set of bidirectional lanes and provides a base lane set and an expanded lane set of bidirectional lanes to support communications with the memory module and the expansion memory card via the expansion connector.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: a first memory card that includes: a memory module connector to connect with a first memory module; an expansion connector to connect with an expansion memory card; a PCIe interface to connect to a host; and a lane distributor on the first memory card to interface with a set of bidirectional lanes, the lane distributor comprising a PCIe switch to operate a base lane set and an expanded lane set of bidirectional lanes to support communications with the memory module via the memory module connector and the expansion memory card via the expansion connector; and a second memory card that includes: a memory module connector to connect a second memory module; an expansion connector to connect via the expansion connector of the first memory card; and a controller to coordinate operation of the memory module based on signals received on the expanded lane set of the bidirectional lanes, wherein the memory module of the second memory card is connectable to the host via the PCIe interface of the first memory card. 2. The apparatus of claim 1 , wherein the bidirectional lanes include serial input and output capabilities to access a Peripheral Component Interconnect Express (PCIe) bus. 3. The apparatus of claim 1 , further comprising an expansion memory card connected to a second expansion connector of the first memory card to increase memory capacity of the first memory card. 4. The apparatus of claim 3 , wherein the memory module of the first memory card and the expansion memory card include a solid state memory device for memory storage. 5. The apparatus of claim 4 , wherein the first memory card includes a redundant array of independent disks (RAID) controller to manage redundant memory storage for the memory module of the first memory card and the expansion memory card. 6. The apparatus of claim 1 , wherein the first memory card includes a fan arranged between the memory module and an expansion memory card in the expansion connector of the first memory card to provide cooling to the memory module and the expansion memory card. 7. An system, comprising: a memory card that includes M.2 memory module integrated into the memory card; an M.2 expansion memory card connected via an expansion connector to the memory card; a sense pin to signal that the expansion memory card is connected to the expansion connector; and a lane distributor on the memory card to interface with a set of bidirectional lanes and to provide a base lane set dedicated to the integrated M.2 memory module and an expanded lane set of bidirectional lanes to support communications with the expansion memory card, the lane distributor to receive input from the sense pin and dynamically deploy the bidirectional lanes based on a number of expansion memory cards connected to the memory card. 8. The system of claim 7 , wherein the bidirectional lanes are serial input and output communications connections to interface with a Peripheral Component Interconnect Express (PCIe) bus. 9. The system of claim 7 , wherein the lane distributor comprises a PCIe switch to interface with the set of bidirectional lanes. 10. The system of claim 7 , further comprising a system management bus to provide an input port to detect the connection of the expansion memory card with the memory card. 11. The system of claim 7 , further comprising a root port to interface with the lane distributor and the memory module via the expansion connector and to negotiate a number of lanes in the set of bidirectional lanes with the memory card. 12. The system of claim 7 , wherein the memory card includes a redundant array of independent disks (RAID) controller to manage redundant memory storage for the memory card and the expansion memory card, the redundant memory storage for the memory card including the solid state memory device and the memory module of the memory card expansion memory card. 13. A system, comprising: a memory card that includes a memory module; an expansion memory card connected via an expansion connector to the memory card; a lane distributor on the memory card to interface with a set of bidirectional lanes to provide a base lane set and an expanded lane set of bidirectional lanes, wherein the base lane set supports communications with the memory module and the expanded lane set supports communication with the expansion memory card when the expanded memory module is installed; and a root port to provide an interface to a computer via the set of bidirectional lanes; wherein the lane distributor is to, upon power up, dynamically assign the bidirectional lanes in a PCIe tree hierarchy, in cooperation with the root port, based on a number of expansion memory cards connectable to the memory card via the expansion connector. 14. The system of claim 13 , wherein the memory card includes a redundant array of independent disks (RAID) controller to manage redundant memory storage for the memory card and the expansion memory card, the redundant memory storage for the memory card including the solid state memory device and the memory module of the memory card expansion memory card. 15. The apparatus of claim 1 , wherein the memory module of the first memory card is integrated into the first memory card, with the base lane set being dedicated to the integrated memory module. 16. The apparatus of claim 1 , further comprising: four M.2 expansion memory cards connected to the expansion connector of the first memory card, wherein the memory module of the first memory card comprises four M.2 memory modules integrated into the first memory card; and wherein each of the memory module of the first memory card and the four M.2 expansion memory cards comprise a solid state drive (SSD) such that eight SSDs are connected to the single PCIe interface of the first memory card. 17. The apparatus of claim 1 , wherein the base lane set is dedicated to the memory module of the first memory card and the expanded lane set is dynamically deployed to support an expansion memory card when connected to the expansion connector. 18. The apparatus of claim 6 , further comprising a support on the first memory card to support the second memory card at a point away from the expansion connector of the first memory card. 19. The system of claim 7 , comprising four integrated M.2 memory modules and four M.2 expansion memory cards, each comprising a solid state drive (SSD) such that eight SSDs are connected to a single PCIe interface of the memory card. 20. The system of claim 7 , wherein the expansion memory card is configured as a daughter card to the memory card.

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What does patent US10545901B2 cover?
An apparatus includes a memory card that includes at least one memory module and an expansion connector to connect with at least one expansion memory card. A lane distributor on the memory card interfaces with a set of bidirectional lanes and provides a base lane set and an expanded lane set of bidirectional lanes to support communications with the memory module and the expansion memory card vi…
Who is the assignee on this patent?
Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification G06F13/4068. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 28 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).