Memory device, memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-10545820-B2
Application number	US-201615154277-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	Apr 12, 2012
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.

First claim

What is claimed is:

1. A synchronous dynamic random access memory (SDRAM) device comprising:
a memory cell array including a plurality of memory cells;
a clock pin receiving a clock signal;
a plurality of data pins receiving write data;
a plurality of command/address pins receiving command/address signals comprising a write command and a write address, wherein the write address indicates a location of the memory cell array for the write data to be written into;
a data masking pin receiving a data. masking signal, wherein the data masking signal indicates a first portion of the write data to he masked, wherein the first portion of the write data is addressed by the write address to be written into a first portion of the memory cell array;
a write command determination unit configured to determine whether the write command is a normal write command or a read modify write command, wherein the read modify write command receives the data masking signal along with the write data for masking the first portion of the write data;
a data modulation unit, wherein if the write command is determined to be the read modify write command, is configured to generate modulation data by reading out first read data from the first portion of the memory cell array and replacing the first portion of write data with the first read data, and the size of the modulation data being equal to the size of the write data,
wherein the modulation data comprises the first read data combined with a second portion of the write data, and the second portion of the write data is a portion of write data other than the first portion of the write data;
an error correction. code (ECC) engine configured to generate a parity; and
a writing unit configured to write at least the second portion of the write data and the parity into the memory cell array if the write command is determined to be the read modify write command.

2. The SDRAM device of claim 1 , wherein the writing unit is further configured to write back the first read data into the first portion of the memory cell array.

3. The SDRAM device of claim 1 , wherein the data masking signal is inputted in synchronization with receipt of the first portion of the write data to be masked.

4. The SDRAM device of claim 1 , further comprising:
a parity region including a plurality of memory cells,
wherein a parity of the modulation data is written into the parity region if the write command is determined to be the read modify write command, and a parity of the write data is written into the parity region if the write command is determined to be the normal write command.

5. The SDRAM device of claim 1 , wherein the normal write command and the read modify write command are distinguished from each other by at least one of the command/address signals.

6. The SDRAM device of claim 5 , wherein the normal write command and the read modify write command are distinguished from each other by keeping at least one of the command/address signals with a logic level low at a rising edge of the clock signal of the write command for the normal write command and with a logic level high at a rising edge of the clock signal of the write command for the read modify write command respectively.

7. The SDRAM device of claim 1 , wherein the modulation data has a hit-size corresponding to the smallest encoding unit of the ECC engine.

8. The SDRAM device of claim 1 , wherein the SDRAM device, if the write command is determined to be the read modify write command, is configured to enable a first column select signal for reading the first portion of the memory cell array and thereafter to enable a second column select signal for writing at least the second portion of write data into the memory cell array.

9. The SDRAM device of claim 8 , wherein the SDRAM device, if the write command is determined to be the read modify write command, is configured to enable a first column select signal for reading the first portion of the memory cell array before receiving the data masking signal.

10. The SDRAM device of claim 8 , wherein the SDRAM device, if the write command is determined to be the read modify write command, is further configured to enable a third column select signal for writing a parity of the modulation data into a parity region.

11. The SDRAM device of claim 1 , wherein the SDRAM device, if the write command is determined to be the normal write command, is configured to enable both a first column select signal and a second column select signal for writing the first portion of the write data and the second portion of the write data respectively.

12. The SDRAM device of claim 11 , wherein the SDRAM device, if the write command is determined to be the normal write command, is further configured to enable a third. column select signal at a same timing with the first and second column select signals for writing a parity of the write data into a parity region.

13. A method of writing data in a synchronous dynamic random access memory (SDRAM) device including an error correction code (ECC) engine, the method comprising:
receiving command/address signals comprising a write command and a write address;
receiving data signals comprising write data, wherein the write data is written into a memory cell array of the SDRAM device based on the write command and the write address;
receiving a data masking signal indicating a first portion of the write data to be masked, wherein the first portion of the write data is addressed by the write address to be written into a first portion of the memory cell array;
determining whether the write command is a read modify write command or a normal write command based on at least one of the command/address signals;
reading the first portion of the memory cell array to produce a first read data if the write command is the read modify write command;
generating modulation data by replacing the first portion of the write data with the first read data, wherein the size of the modulation data is equal to the size of the write data,
wherein the modulation data comprises the first read data combined with a second portion of the write data, and the second portion of the write data is a portion of write data other than the first portion of the write data;
encoding a parity of the modulation data by using the ECC engine; and
writing at least the second portion of the write data and the parity of the modulation data into the memory cell array and a parity region respectively if the write command is determined to be the read modify write command,
wherein, if the write command is determined to be the read modify write command, at least the second portion of the write data is written into the memory cell array after the data masking signal is received.

14. The method of claim 13 , wherein the method further includes writing back the first read data into the first portion of the memory cell array.

15. The method of claim 13 , wherein the data masking signal is inputted in synchronization with receipt of the first portion of the write data to be masked.

16. The method of claim 13 , wherein the method further includes generating a parity of the write data if the write command is the normal write command.

17. The method of claim 13 , wherein the method further includes writing the write data and the parity of the write data into the memory cell array and the parity region respectively if the write command is the normal write command.

18. The method of claim 13 , wherein the modulation data has a bit-size corresponding to the smallest encoding unit of the E

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jong-Wook

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H03M13/05 Primary

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title