Injection-locked phase lock loop circuit

Patent metadata

Field	Value
Publication number	US-10541694-B2
Application number	US-201916238092-A
Country	US
Kind code	B2
Filing date	Jan 2, 2019
Priority date	Jul 27, 2016
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.

First claim

What is claimed is:

1. A phase lock loop (PLL) circuit comprising:
a phase frequency detector circuit that outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal;
a charge pump circuit that outputs a pulse signal based on the detection signal;
a loop filter that outputs a control voltage based on the pulse signal;
a voltage-controlled oscillator circuit that includes a ring oscillator, in which a plurality of delay element units including a plurality of delay elements connected in parallel are connected in series in a ring, that receives the control voltage and controls a frequency of an output signal of the ring oscillator based on the control voltage, and that receives the detection signal and controls a phase of the output signal, independently of controlling the frequency of the output signal, by controlling an active number of the delay elements out of the plurality of delay elements based on the detection signal; and
a frequency divider circuit that divides the output signal to generate the feedback signal and outputs the feedback signal.

2. The PLL circuit according to claim 1 , wherein
The voltage-controlled oscillator circuit includes a switch unit that sets, in a first state where a second phase of the feedback signal is a first phase difference behind a first phase of the reference signal and based on the detection signal, first delay elements out of the plurality of delay elements in an operating state for a first period corresponding to the first phase difference, and sets, in a second state where the second phase is a second phase difference ahead, of the first phase and based on the detection signal, second delay elements out of the plurality of delay elements in a non-operating state for a second period corresponding to the second phase difference.

3. The PLL circuit according to claim 2 , wherein
the detection signal includes a first signal and a second signal,
the switch unit has a first switch unit connected to power supply terminals of the plurality of delay elements and a second switch unit connected to ground terminals of the plurality of delay elements,
the first switch unit and the second switch unit each include;
a first transistor that is controlled based on the first signal and a second transistor that is connected in series to the first transistor and is controlled based on the second signal, the first transistor and the second transistor being provided on a first current path, which supplies a current based on a power supply voltage to the first delay elements; and
a third transistor that is controlled based on the first signal and a fourth transistor that is connected in parallel to the third transistor and is controlled based on the second signal, the third transistor and the fourth transistor being provided on a second current path, which supplies a current based on the power supply voltage to the second delay elements,

in the first state, the first transistor and the second transistor turn on to supply the current to the first delay elements, and after the first period, the first transistor remains on and the second transistor changes from, on to off to cut off supplying of the current to the first delay elements, and
in the second state, the third transistor and the fourth transistor turn off to cut off supplying of the current to the second delay elements, and after the second time, the third transistor remains off and the fourth transistor changes from off to on to supply the current to the second delay elements.

4. The PLL circuit according to claim 3 , wherein
the first switch unit and the second switch unit each include a fifth transistor that is connected in series to the third transistor and is controlled based on the second signal and a sixth transistor that is connected in series to the fourth transistor and is controlled based on the first signal, and
in the first state, the third transistor and the fifth transistor are both on or the fourth transistor and the sixth transistor are both on, and in the second state, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all off.

5. The PLL circuit according to claim 3 , wherein
the second switch unit includes a seventh transistor, which is connected to the first transistor or the second transistor and controls a magnitude of the current flowing to the first current path based on the control voltage, and an eighth transistor, which is connected to the third transistor or the fourth transistor and controls a magnitude of the current flowing to the second current path based on the control voltage, and
the voltage-controlled oscillator circuit includes a current supply circuit that supplies a first current to the first current path between the first transistor or the second transistor and the seventh transistor when the first delay elements are in the non-operating state, and supplies the first current to the second current path between the third transistor or the fourth transistor and the eighth transistor when the second delay elements are in the non-operating state.

6. The PLL circuit according to claim 3 , wherein
the first switch unit and the second switch unit each include a ninth transistor that is provided on a third current path, which supplies a current to third delay elements out of the plurality of delay elements, and becomes on irrespective of the first signal and the second signal.

7. The PLL circuit according to claim 6 , wherein
The voltage-controlled oscillator circuit includes:
a first capacitor that is connected to both ends of the first delay elements on the first current path;
a second capacitor that is connected to both ends of the second delay elements on the second current path; and
a third capacitor that is connected to both ends of the third delay elements on the third current path.

8. The PLL circuit according to claim 1 , further comprising:
a frequency overshoot suppression circuit that includes a capacitor, whose held voltage rises as a second frequency of the feedback signal approaches a first frequency of the reference signal, and that invalidates the detection signal supplied to the voltage-controlled oscillator circuit until the held voltage exceeds a threshold value.

Assignees

• Socionext Inc

Inventors

• Sato Hajime
• Aruga Kenta

Classifications

• H03L7/101

  using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence) · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/0997

  Controlling the number of delay elements connected in series in the ring oscillator · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title