SPWM with DC offset based on total energy reduction

Patent metadata

Field	Value
Publication number	US-10541602-B2
Application number	US-201816175254-A
Country	US
Kind code	B2
Filing date	Oct 30, 2018
Priority date	Oct 30, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

Various examples related to sinusoidal pulse width modulation (SPWM) techniques for harmonic and electromagnetic interference (EMI) noise suppression are provided. In one example, a method includes applying a DC offset to a sinusoidal modulation waveform to change an average duty cycle of a switching circuit; and controlling switching of an array of switches of the switching circuit based at least in part upon the offset sinusoidal modulation waveform and a carrier waveform, thereby reducing total energy. In another example, a system includes a switching circuit with an array of semiconductor switches that control application of a voltage source to a load; and controller circuitry that can control switching of the array of semiconductor switches by applying a DC offset to a sinusoidal modulation waveform to change an average duty cycle of the switching circuit.

First claim

Therefore, at least the following is claimed:

1. A method for electromagnetic interference energy mitigation, comprising:
applying a DC offset to a sinusoidal modulation waveform to change an average duty cycle of a switching circuit to less than 0.5 or greater than 0.5, the average duty cycle based upon a modulation index of the sinusoidal modulation waveform; and
controlling switching of an array of switches of the switching circuit to operate with the average duty cycle using sinusoidal pulse width modulation (SPWM) based at least in part upon the offset sinusoidal modulation waveform and a carrier waveform, thereby reducing total energy of an output of the array of switches.

2. The method of claim 1 , wherein a modulation index range of the switching circuit is less than 0.6.

3. The method of claim 2 , wherein the modulation index range is less than 0.4.

4. The method of claim 1 , wherein the average duty cycle is less than 0.5.

5. The method of claim 1 , wherein the average duty cycle is less than a half of the modulation index of the sinusoidal modulation waveform.

6. The method of claim 5 , wherein the DC offset of the sinusoidal modulation waveform is limited by the modulation index of the sinusoidal modulation waveform.

7. The method of claim 5 , wherein the modulation index is adjusted to achieve a defined THD (total harmonic distortion) without saturation.

8. The method of claim 1 , wherein the carrier waveform is a sawtooth waveform or a triangular waveform.

9. The method of claim 1 , wherein the switching circuit is a half bridge circuit, an H-bridge circuit or a three-phase bridge circuit.

10. A system, comprising:
a switching circuit comprising an array of semiconductor switches that control application of a voltage source to a load; and
controller circuitry configured to control switching of the array of semiconductor switches using sinusoidal pulse width modulation (SPWM) by applying a DC offset to a sinusoidal modulation waveform to change an average duty cycle of the switching circuit to less than 0.5 or greater than 0.5, the average duty cycle based upon a modulation index of the sinusoidal modulation waveform, thereby reducing total energy of an output of the array of switches.

11. The system of claim 10 , wherein the average duty cycle is less than a half of the modulation index of the sinusoidal modulation waveform.

12. The system of claim 11 , wherein the DC offset of the sinusoidal modulation waveform is limited by the modulation index of the sinusoidal modulation waveform.

13. The system of claim 11 , wherein the modulation index is adjusted to achieve a defined THD (total harmonic distortion) without saturation.

14. The system of claim 12 , wherein the modulation index is adjusted to reduce total demand distortion (TDD).

15. The system of claim 10 , wherein the carrier waveform is a sawtooth waveform or a triangular waveform.

16. The system of claim 15 , wherein switching of the array of semiconductor switches is controlled with the SPWM using regular sampling with a stepped sinusoidal modulation waveform or natural sampling with a sine wave sinusoidal modulation waveform.

17. The system of claim 16 , wherein the natural sampling is symmetric or asymmetric.

18. The system of claim 10 , wherein the switching circuit is a half bridge circuit, an H-bridge circuit or a three-phase bridge circuit.

19. The system of claim 10 , wherein a modulation index range is less than 0.6.

20. The system of claim 19 , wherein the average duty cycle is equal to or less than half of the modulation index.

Assignees

• Univ Florida

Inventors

• Wang Shuo
• Zhao Hui
• Yang Le
• Zhang Yingjie

Classifications

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• H02M7/53871

  with automatic control of output voltage or current · CPC title

• H02M1/44 Primary

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M7/5395

  by pulse-width modulation · CPC title

• H02M7/53873

  with digital control · CPC title