System transparent retimer

Patent metadata

Field	Value
Publication number	US-10540314-B2
Application number	US-201916265845-A
Country	US
Kind code	B2
Filing date	Feb 1, 2019
Priority date	Jul 17, 2015
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operational state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward data it receives in both downstream and upstream directions of the link without frequency alteration.

First claim

What is claimed is:

1. A method of transferring data between interconnected devices, comprising:
at a retimer circuit configured to couple a host and a device electrically:
monitoring first data and second data received from the host and the device, respectively, the host and the device being electrically coupled to each other via an interconnect;
obtaining a host side band detection signal indicating a first data speed of the first data;
obtaining a device side band detection signal indicating a second data speed of the second data; and
determining an operational state of the retimer based on (1) at least one of the monitored first data and the monitored second data and (2) at least one of the host side band detection signal and the device side band detection signal.

2. The method of claim 1 , further comprising:
obtaining a host side receiver status signal indicating at least a far-end impedance of a receiver in the host; and
obtaining a device side receiver status signal indicating at least a far-end impedance of a receiver in the device, wherein the operational state of the retimer is determined based on at least one of the host side receiver status and the device side receiver status.

3. The method of claim 1 , wherein determining the operational state of the retimer further comprises determining a negotiated link speed for communicating data between the host and the device.

4. The method of claim 3 , wherein the negotiated link speed is 5 Gbps or 10 Gbps in accordance with a determination of the highest data rates supported by the host and the device.

5. The method of claim 4 , wherein obtaining the host side band detection signal further comprises:
receiving one or more high speed signaling handshake messages;
determining a loss of the high speed signaling handshake messages; and
determining the first data speed and the negotiated link speed based on the loss of the high speed signaling handshake messages.

6. The method of claim 4 , wherein the negotiated link speed is 5 Gbps, the method further comprising:
determining that (1) a first highest data rate supported by a first one of the host and device is 5 Gbps and (2) that a second highest data rate supported by a second one of the host and device is 10 Gbps, the second one of the host and device being distinct from the first one of the host and device.

7. The method of claim 3 , further comprising enabling a communication link between the host and the device according to the negotiated link speed.

8. The method of claim 7 , further comprising:
training a data path associated with the communication link, including at least one of:
training an equalizer configured to condition the first data received from the host or the second data received form the device; and
training a clock data recovery (CDR) circuit configured to generate a clock signal based on the negotiated link speed.

9. The method of claim 1 , further comprising:
generating, by a clock data recovery circuit, a recovered clock having a clock rate matching a rate of a clock signal in the first data; and
providing, by the clock data recovery circuit, the recovered clock to a first transmitter to control a transmission rate of the second data to the host.

10. The method of claim 9 , wherein the clock data recovery circuit further includes an inductor capacitor oscillator that is tunable and configured to generate the recovered clock.

11. A retimer circuit for transferring data between interconnected devices, comprising:
a host receiver circuit configured to receive first data from a host and transmit the first data to a device via a device transmitter circuit, the host and the device being electrically coupled to each other via an interconnect;
a host transmitter circuit configured to receive second data from the device via a device receiver circuit and transmit the second data to the host; and
a controller coupled to the host receiver circuit, the device transmitter circuit, the device receiver circuit, and the host transmitter circuit, the controller being configured to:
obtain a host side band detection signal indicating a first data speed of the first data;
obtain a device side band detection signal indicating a second data speed of the second data; and
determine an operational state of the retimer based on (1) at least one of the monitored first data and the monitored second data and (2) at least one of the host side band detection signal and the device side band detection signal.

12. The retimer circuit of claim 11 , further comprising:
the device receiver circuit configured to receive the second data from the device and transmit the second data to the host via the host transmitter circuit, the device receiver circuit being distinct from the host receiver circuit; and
the device transmitter circuit configured to receive the first data from the host via the host receiver circuit and transmit the first data to the device, the device transmitter circuit being distinct from the host transmitter circuit.

13. The retimer circuit of claim 11 , further comprising:
a clock data recovery circuit configured to generate a clock signal, wherein the host transmitter circuit is configured to modify a second data speed of the second data according to a frequency of the clock signal generated by the clock data recovery circuit.

14. The retimer circuit of claim 11 , wherein the host side band detection signal is associated with a first voltage level indicating that a data rate of the first data is selected from one or more predetermined data speeds and a second voltage level indicating that the data rate of the first data is distinct from any of the one or more predetermined data speeds.

15. The retimer circuit of claim 11 , wherein the controller is configured to obtain the host side band detection signal by:
receiving one or more LFPS messages transmitted at a side band from 20 MHz to 50 MHz, the LFPS messages including one or more pulse trains; and
determining a pulse duration of the pulse trains and an idle duration of an electrical idle period between two of the pulse trains, wherein the first data speed of the first data is determined based on the determined pulse and idle durations.

16. The retimer circuit of claim 11 , wherein the retimer circuit is configured, in accordance with the operational state of the retimer, to transmit the first data to the device, and transmit the second data to the host.

17. The retimer circuit of claim 11 , wherein the operational state of the retimer is associated with a combined retimer operating state, and the controller is configured to map a group of host and device operational states to the combined retimer operating state.

18. The retimer circuit of claim 17 , wherein the group of host and device operational states includes (1) a Polling.LFPS state configured to synchronize operations between the host and the device after exiting from a receiver detection state and (2) a plurality of power saving states.

19. The retimer circuit of claim 11 , wherein the controller is configured to detect a connection of the host with the retimer circuit, and the operational state is determined in response to the detection of the connection of the host with the retimer circuit.

20. The retimer circuit of claim 11 , wherein the controller is configured to detect a message in the first data provided by the host and determine the operational state of the retimer based on the message.

Assignees

• Parade Tech Ltd

Inventors

• Chen Jian
• Qu Ming
• Lee Kc
• Yuan Zhengyu
• Ouyang Qing

Classifications

• G06F11/3051

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/151

  Cross-Sectional Technologies · mapped topic