Module based data transfer

Patent metadata

Field	Value
Publication number	US-10540303-B2
Application number	US-201816236971-A
Country	US
Kind code	B2
Filing date	Dec 31, 2018
Priority date	Mar 6, 2015
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the data sent on a memory bus by the first memory module into a second memory module. The direct transfer of data between the first and second memory modules reduces power consumption and increases performance.

First claim

What is claimed:

1. A method of data transfer comprising:
sending a read request to a first memory component;
sending a write request to a second memory component, wherein the write request comprises an indicator that the second memory component is to capture data sent directly from the first memory component to the second memory component;
in response to the read request, sending the data from the first memory component across a bus, wherein the bus electrically couples the first memory component to the second memory component; and
in response to the write request, storing the data from the bus into the second memory component.

2. The method of claim 1 , wherein the first memory component and the second memory component comprises separate memory dies within a memory module.

3. The method of claim 1 , wherein the first memory component and the second memory component comprises separate memory dies in separate memory modules.

4. The method of claim 1 , wherein the first memory component and the second memory component comprises separate memory modules, each comprising a plurality of non-volatile memory devices.

5. The method of claim 1 , further comprising:
performing an initialization process for a direct transfer of the data from the first memory component to the second memory component.

6. The method of claim 1 , further comprising:
accessing the data via the bus using a buffer; and
performing error checking on the data using the buffer.

7. The method of claim 6 , further comprising:
in response to determining an error based on the error checking, sending an error indicator to the second memory component.

8. A system comprising:
a processor;
a first memory component;
a second memory component; and
a bus electrically coupling the processor, the first memory component and the second component, wherein the processor is configured to send a read request to the first memory component and to send a write request to the second memory component, wherein the write request comprises an indicator that the second memory component is to capture data sent directly from the first memory component to the second memory component, wherein, in response to the read request, the first memory component is configured to send the data from the first memory component across the bus, and wherein, in response to the write request, the second memory component is configured to store the data from the bus into the second memory component.

9. The system of claim 8 , wherein the first memory component and the second memory component comprises separate memory dies within a memory module.

10. The system of claim 8 , wherein the first memory component and the second memory component comprises separate memory dies in separate memory modules.

11. The system of claim 8 , wherein the first memory component and the second memory component comprises separate memory modules, each comprising a plurality of non-volatile memory devices.

12. The system of claim 8 , wherein the processor is further configured to perform an initialization process for a direct transfer of the data from the first memory component to the second memory component.

13. The system of claim 8 , further comprising:
a buffer, wherein the processor is further configured to:
access the data via the bus using the buffer; and
perform error checking on the data using the buffer.

14. The system of claim 13 , wherein, in response to determining an error based on the error checking, the processor is further configured to send an error indicator to the second memory component.

15. A method comprising:
receiving a copy request to copy data, wherein the copy request comprises a source address and a destination address;
determining that a first memory component associated with the source address and a second memory component associated with the destination address are electrically coupled to a bus;
in response to determining the first memory component and the second memory component are electrically coupled to the bus, sending a read request to the first memory component, wherein, in response to the read request, the first memory component is configured to send data associated with the source address across the bus; and
sending a write request to the second memory component, wherein the write request comprises an indicator that the second memory component is to capture data sent directly from the first memory component to the second memory component, and wherein, in response to the write request, the second memory component is configured to store the data from the memory bus into the destination address of the second memory component.

16. The method of claim 15 , wherein the first memory component and the second memory component comprises separate memory dies within a memory module.

17. The method of claim 15 , wherein the first memory component and the second memory component comprises separate memory dies in separate memory modules.

18. The method of claim 15 , wherein the first memory component and the second memory component comprises separate memory modules, each comprising a plurality of non-volatile memory devices.

19. The method of claim 15 , further comprising:
accessing the data via the bus using a buffer; and
performing error checking on the data using the buffer.

20. The method of claim 19 , further comprising:
in response to determining an error based on the error checking, sending an error indicator to the second memory component.

Assignees

• Rambus Inc

Inventors

• Woo Steven
• Secker David

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F13/1673 Primary

  using buffers · CPC title