Virtual host controller for a data processing system

Patent metadata

Field	Value
Publication number	US-10540301-B2
Application number	US-201715721871-A
Country	US
Kind code	B2
Filing date	Sep 30, 2017
Priority date	Jun 2, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

One embodiment provides an apparatus comprising a first processor to execute a function driver for a peripheral having a first bus interface and virtualized host controller interface logic to provide a protocol interface associated with the first bus interface to the function driver to enable the function driver to control a set of peripherals connected via at least a second bus interface, the second bus interface different from the first bus interface.

First claim

What is claimed is:

1. An apparatus comprising:
a first processor to execute a function driver for a peripheral having a first bus interface; and
virtualized host controller interface logic to provide a first protocol interface associated with the first bus interface to the function driver to enable the function driver to control a set of peripherals connected via at least a second bus interface, the second bus interface different from the first bus interface, wherein:
the virtualized host controller interface logic includes a first node and a second node, the first node to provide the first protocol interface to the function driver,
the second node is to connect to a first peripheral in the set of peripherals via the second bus interface and communicate with the first peripheral via a second protocol interface associated with the second bus interface, and
the first node and the second node are to communicate over a fourth bus via a transport agnostic protocol that is independent of the transport protocol of the fourth bus.

2. The apparatus as in claim 1 , wherein the set of peripherals includes a biometric sensor.

3. The apparatus as in claim 2 , wherein biometric sensor includes a fingerprint sensor.

4. The apparatus as in claim 2 , wherein the set of peripherals includes a camera.

5. The apparatus as in claim 4 , wherein the first bus interface is a universal serial bus (USB) interface.

6. The apparatus as in claim 5 , wherein the second bus interface is a serial peripheral interface (SPI), a general-purpose input/output (GPIO) interface, an inter-integrated circuit (I2C) interface, or a Universal Asynchronous Receiver/Transmitter (UART) interface.

7. The apparatus as in claim 6 , wherein the second node is to connect to a second peripheral in the set of peripherals via a third bus interface and the third bus interface is a serial peripheral interface (SPI), a general-purpose input/output (GPIO) interface, an inter-integrated circuit (I2C) interface, or a Universal Asynchronous Receiver/Transmitter (UART) interface, and the second node is to communicate with the second peripheral via a third protocol interface associated with the third bus interface.

8. The apparatus as in claim 7 , wherein the fourth bus is a peripheral component interconnect (PCI) bus or a PCI express bus.

9. The apparatus as in claim 1 , wherein the set of peripherals connected via at least the second bus interface includes a non-volatile storage device.

10. The apparatus as in claim 1 , wherein the virtualized host controller interface logic includes a first node enabled via the first processor, the first node to provide the first protocol interface to the function driver and a second node to connect to the set of peripherals via at least the second bus interface, the second node enabled via a second processor.

11. The apparatus as in claim 10 , wherein the first processor is to execute a first operating system and the second processor is to execute a second operating system different from the first operating system.

12. A data processing system comprising:
a first non-transitory machine-readable medium storing first instructions;
a first processor configured to execute the first instructions, the first instructions to enable a first node of a host controller interface;
a second non-transitory machine-readable medium storing second instructions;
a second processor configured to execute the second instructions, the second instructions to enable a second node of the host controller interface;
wherein the host controller interface is to provide a universal serial bus (USB) interface for a first non-USB peripheral via the first node;
wherein the host controller interface is to connect with the first non-USB peripheral via the second node; and
wherein the first node and the second node are to communicate via a transport agnostic link.

13. The data processing system as in claim 12 , the second node to connect with the first non-USB peripheral via a first bus interface, the first bus interface including a serial peripheral interface (SPI), a general-purpose input/output (GPIO) interface, an inter-integrated circuit (I2C) interface, or a Universal Asynchronous Receiver/Transmitter (UART) interface.

14. The data processing system as in claim 13 , the second node to connect with a second non-USB peripheral via a second bus interface, the second bus interface including a serial peripheral interface (SPI), a general-purpose input/output (GPIO) interface, an inter-integrated circuit (I2C) interface, or a Universal Asynchronous Receiver/Transmitter (UART) interface.

15. The data processing system as in claim 14 , wherein the first bus interface differs from the second bus interface.

16. The data processing system as in claim 15 , the second node to connect with a third non-USB peripheral via a third bus interface different from the first bus interface and the second bus interface.

17. The data processing system as in claim 16 , wherein the first non-USB peripheral, second non-USB peripheral, or third non-USB peripheral includes a non-volatile storage device or a bio sensor.

18. The data processing system as in claim 16 , the first node and the second node to communicate via the transport agnostic link over a fourth bus, the fourth bus having a transport protocol independent of the transport protocol of the transport agnostic link.

19. A non-transitory machine-readable medium storing instructions which, when executed on one or more processors cause the one or more processors to perform operations comprising:
enabling a first node of a virtualized host controller interface, the first node providing a first protocol interface for a set of peripherals;
initiating establishment of a transport agnostic message link with a second node of the virtualized host controller interface, the second node connected with the set of peripherals via a second protocol interface;
receiving a set of messages from the second node via the transport agnostic link; and
translating the set of messages to the first protocol interface.

20. The non-transitory machine-readable medium as in claim 19 , the operations additionally comprising:
enabling the second node of a virtualized host controller interface, the second node connected with a set of peripherals via a second protocol interface;
receiving initiation of the transport agnostic message link with the first node of the virtualized host controller interface;
receiving signals from the set of peripherals via the second protocol interface; and
sending translated signals from the set of peripherals over the transport agnostic message link to the first node.

Assignees

• Apple Inc

Inventors

• Wilson Daniel B
• Deandrea Scott M
• Yepez Roberto G

Classifications

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F13/107 Primary

  Terminal emulation · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title