Accelerated execution of execute instruction target

Patent metadata

Field	Value
Publication number	US-10540183-B2
Application number	US-201715798887-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Jan 19, 2015
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

As disclosed herein a method, executed by a processor, for accelerated instruction execution includes retrieving an execute instruction including a register reference and a reference to a target instruction, retrieving the target instruction, decoding the execute instruction using an instruction pipeline, decoding the target instruction using the instruction pipeline, associating the register reference to the target instruction, and executing the target instruction using the register reference as a source operand modifier. The instruction pipeline is configured such that it allows the target instruction to continue processing without waiting for the register reference to be resolved. The contents of the referenced register may be retrieved in a later stage of the instruction pipeline, and the target instruction may be modified and executed. An apparatus corresponding to the described method is also disclosed herein.

First claim

What is claimed is:

1. A method, executed by a computer, for accelerated execution of an execute instruction, the method comprising:
retrieving an execute instruction comprising a register reference and a reference to a target instruction;
retrieving the target instruction;
decoding the execute instruction using one or more decoding stages in an instruction pipeline;
decoding the target instruction using one or more decoding stages in the instruction pipeline;
associating the register reference to the target instruction as an additional source operand modifier; and
executing the target instruction using the register reference as the additional source operand modifier; and
assigning one or more resources based, at least in part, on an assumed length operand of the target instruction.

2. The method of claim 1 , wherein the instruction pipeline is further configured to continue processing the target instruction without waiting for the register reference to be resolved.

3. The method of claim 1 , wherein contents of a register indicated by the register reference are obtained using a double issue operation, if a number of sources for the target instruction exceeds a specified limit.

4. The method of claim 1 , wherein a part of the target instruction is modified in a later stage of the instruction pipeline, using contents of a register indicated by the register reference.

5. The method of claim 4 , wherein the part of the target instruction corresponds to one of a length operand, an immediate operand, a mask operand, and a register.

6. The method of claim 1 , wherein the assumed length operand of the target instruction is altered by logically ORing the assumed length operand with contents of a register indicated by the register reference.

7. The method of claim 6 , wherein the contents comprise one or more bits from the register.

8. The method of claim 1 , wherein the target instruction is executed without modification if the register reference is zero.

9. An apparatus for accelerated execution of an execute instruction, the apparatus comprising:
an instruction retrieval module configured to retrieve an execute instruction comprising a register reference and a reference to a target instruction;
the instruction retrieval module further configured to retrieve the target instruction;
an instruction pipeline configured to decode the execute instruction;
the instruction pipeline further configured to decode the target instruction;
the instruction pipeline further configured to modify the target instruction by associating the register reference to the target instruction as an additional source operand modifier; and
an execution unit configured to execute the target instruction using the register reference as the additional source operand modifier; and
the instruction pipeline further configured to assign one or more resources based, at least in part, on an assumed length operand of the target instruction.

10. The apparatus of claim 9 , wherein the instruction pipeline is further configured to continue processing the target instruction without waiting for the register reference to be resolved.

11. The apparatus of claim 9 , wherein contents of a register indicated by the register reference are obtained using a double issue operation, if a number of sources for the target instruction exceeds a specified limit.

12. The apparatus of claim 9 , wherein a part of the target instruction is modified in a later stage of the instruction pipeline, using contents of a register indicated by the register reference.

13. The apparatus of claim 12 , wherein the part of the target instruction corresponds to one of a length operand, an immediate operand, a mask operand, and a register.

14. The apparatus of claim 9 , wherein the assumed length operand of the target instruction is altered by logically ORing the assumed length operand with contents of a register indicated by the register reference.

15. The apparatus of claim 14 , wherein the contents comprise one or more bits from the register.

16. The apparatus of claim 9 , wherein the target instruction is executed without modification if the register reference is zero.

Assignees

• IBM

Inventors

• Alexander Khary J
• Busaba Fadi Y
• Curran Brian W
• Hutton David S
• Malley Edward T
• Prasky Brian R
• Rell Jr John G

Classifications

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/3822 Primary

  Parallel decoding, e.g. parallel decode units · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title