Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment

Patent metadata

Field	Value
Publication number	US-10540170-B2
Application number	US-201816128920-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	Dec 8, 2016
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

First claim

What is claimed is:

1. A computer program product, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by at least one processor to perform:
dividing a plurality of Input/Output (I/O) enclosures into a first set of I/O enclosures and a second set of I/O enclosures;
performing concurrent code activation for the first set of I/O enclosures by:
sending first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored by each I/O enclosure management engine;
activating an update image on the first set of I/O enclosures, wherein the update image contains a first image file for firmware and a second image file for a Field-Programmable Gate Array (FPGA), and wherein activating the update image updates at least one of the firmware and the FPGA; and
sending second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed; and

performing concurrent code activation for the second set of I/O enclosures.

2. The computer program product of claim 1 , wherein the program code is executable by at least one processor to perform:
performing high-level system pre-checks on the first set of I/O enclosures and the second set of I/O enclosures.

3. The computer program product of claim 1 , wherein the program code is executable by at least one processor to perform:
activating the update image on the second set of I/O enclosures.

4. The computer program product of claim 1 , wherein an I/O enclosure management engine on a server node of the plurality of server nodes updates a flag for each of the first set of I/O enclosures based on receiving one of a first notification of the first notifications and a second notification of the second notifications.

5. The computer program product of claim 1 , wherein the plurality of server nodes are coupled to a computing system storing a code load management engine, and wherein the plurality of server nodes and the computing system comprise nodes in a cloud infrastructure.

6. A computer system, comprising:
one or more processors, one or more computer-readable memories and one or more computer-readable, tangible storage devices; and
program instructions, stored on at least one of the one or more computer-readable, tangible storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, to perform operations comprising:
dividing a plurality of Input/Output (I/O) enclosures into a first set of I/O enclosures and a second set of I/O enclosures;
performing concurrent code activation for the first set of I/O enclosures by:
sending first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored by each I/O enclosure management engine;
activating an update image on the first set of I/O enclosures, wherein the update image contains a first image file for firmware and a second image file for a Field-Programmable Gate Array (FPGA), and wherein activating the update image updates at least one of the firmware and the FPGA; and
sending second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed; and

performing concurrent code activation for the second set of I/O enclosures.

7. The computer system of claim 6 , wherein the operations further comprise:
performing high-level system pre-checks on the first set of I/O enclosures and the second set of I/O enclosures.

8. The computer system of claim 7 , wherein the operations further comprise:
activating the update image on the second set of I/O enclosures.

9. The computer system of claim 7 , wherein an I/O enclosure management engine on a server node of the plurality of server nodes updates a flag for each of the first set of I/O enclosures based on receiving one of a first notification of the first notifications and a second notification of the second notifications.

10. The computer system of claim 7 , wherein the plurality of server nodes are coupled to a computing system storing a code load management engine, and wherein the plurality of server nodes and the computing system comprise nodes in a cloud infrastructure.

11. A computer-implemented method, comprising:
dividing with a processor of a computing system, a plurality of Input/Output (I/O) enclosures into a first set of I/O enclosures and a second set of I/O enclosures;
performing, with the processor of the computing system, concurrent code activation for the first set of I/O enclosures by:
sending, with the processor of the computing system, first notifications to each I/O enclosure management engine on each of a plurality of server nodes that code activation for the first set of I/O enclosures is starting, wherein errors that disrupt the code activation are ignored by each I/O enclosure management engine;
activating, with the processor of the computing system, an update image on the first set of I/O enclosures, wherein the update image contains a first image file for firmware and a second image file for a Field-Programmable Gate Array (FPGA), and wherein activating the update image updates at least one of the firmware and the FPGA; and
sending, with the processor of the computing system, second notifications to each I/O enclosure management engine on each of the plurality of server nodes that code activation for the first set of I/O enclosures has completed; and

performing, with the processor of the computing system, concurrent code activation for the second set of I/O enclosures.

12. The computer-implemented method of claim 11 , further comprising:
performing, with the processor of the computing system, high-level system pre-checks on the first set of I/O enclosures and the second set of I/O enclosures.

13. The computer-implemented method of claim 11 , further comprising:
activating, with the processor of the computing system, the update image on the second set of I/O enclosures.

14. The computer-implemented method of claim 11 , wherein an I/O enclosure management engine on a server node of the plurality of server nodes updates a flag for each of the first set of I/O enclosures based on receiving one of a first notification of the first notifications and a second notification of the second notifications.

15. The computer-implemented method of claim 11 , wherein the plurality of server nodes are coupled to the computing system storing a code load management engine, and wherein the plurality of server nodes and the computing system comprise nodes in a cloud infrastructure.

Assignees

• IBM

Inventors

• Batchelor Gary W
• Davila Veronica S
• Garcia Enrique Q
• Han Robin
• Kirch Jay T
• Martens Ronald D
• Nguyen Trung N
• Rinaldi Brian A
• Sorenson Todd C

Classifications

• H04L67/34

  involving the movement of software or configuration parameters  (network booting or remote initial program loading [RIPL] G06F9/4416) · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title

• H04L67/10

  in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) · CPC title