Mapping-based wear leveling for non-volatile memory

US10540100B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10540100-B2
Application numberUS-201815949976-A
CountryUS
Kind codeB2
Filing dateApr 10, 2018
Priority dateApr 10, 2018
Publication dateJan 21, 2020
Grant dateJan 21, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: one or more non-volatile memory elements; and a controller configured to: maintain a logical-to-physical mapping for converting logical addresses to physical addresses, the logical-to-physical mapping comprising a group-to-group translation table that provides any-to-any mapping between groups of logical addresses and groups of physical addresses, and one or more mathematical mappings, wherein a mathematical mapping for a group of logical addresses associates individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses; change at least one of the mathematical mappings; and move data based on the changed at least one mapping. 2. The apparatus of claim 1 , wherein changing at least one of the mathematical mappings swaps pairs of physical addresses associated with pairs of logical addresses, and moving the data comprises swapping data values between pairs of physical addresses. 3. The apparatus of claim 2 , wherein swapping data values between pairs of physical addresses comprises delaying individual pair swaps based on a swap frequency target. 4. The apparatus of claim 3 , wherein a group size for a group of physical addresses is based on the swap frequency target. 5. The apparatus of claim 1 , wherein a mathematical mapping comprises a mathematical transformation for determining at least a portion of a physical address based on at least a portion of a logical address, wherein a mathematical transformation comprises an XOR operation with a placement map. 6. The apparatus of claim 5 , wherein changing a mathematical mapping comprises changing the placement map. 7. The apparatus of claim 5 , wherein changing a mathematical mapping comprises changing a single bit of the placement map. 8. The apparatus of claim 5 , wherein changing a mathematical mapping comprises incrementing the placement map in Gray Code order. 9. The apparatus of claim 1 , wherein the controller is further configured to: receive a request to perform a memory operation, the request indicating a logical address; select one of a changed mathematical mapping and an un-changed mathematical mapping to convert the logical address to a physical address; and perform the memory operation at a physical address based on the selected mathematical mapping. 10. The apparatus of claim 9 , wherein selecting a mapping comprises determining whether data has been moved for the logical address of the memory operation request. 11. The apparatus of claim 1 , wherein changing at least one of the mathematical mappings comprises selecting a new mapping based on metadata, the metadata recording wear for logical addresses and wear for physical addresses. 12. The apparatus of claim 1 , wherein the controller is further configured to merge two groups by updating the translation table, determine a new mathematical mapping for the merged group, and move data based on the new mathematical mapping. 13. The apparatus of claim 1 , wherein the controller is further configured to split a group into two groups by updating the translation table. 14. A method comprising: storing a logical-to-physical mapping for converting logical addresses to physical addresses, the logical-to-physical mapping comprising a group-to-group translation table that provides any-to-any mapping between groups of logical addresses and groups of physical addresses, and one or more mathematical mappings, wherein a mathematical mapping for a group of logical addresses associates individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses, a mathematical mapping comprising an XOR map for determining at least a portion of a physical address based on at least a portion of a logical address; changing an XOR map for at least one of the mathematical mappings; and swapping data between physical addresses based on the changed XOR map. 15. The method of claim 14 , wherein swapping data comprises delaying individual pair swaps based on a swap frequency target. 16. The method of claim 15 , wherein a group size for a group of physical addresses is based on the swap frequency target. 17. The method of claim 14 , wherein changing the XOR map comprises incrementing the XOR map in Gray Code order. 18. The method of claim 14 , further comprising: receiving a request to perform a memory operation, the request indicating a logical address; selecting one of a changed XOR map and an un-changed XOR map to convert the logical address to a physical address; and performing the memory operation at a physical address based on the selected XOR map. 19. An apparatus comprising: means for mapping a first portion of a logical address to a group of physical addresses, wherein the means for mapping a first portion of a logical address to a group of physical addresses provides group-to-group, any-to-any mapping between groups of logical addresses and groups of physical addresses; means for applying an XOR mask to a second portion of the logical address to determine a physical address within the group; means for changing the XOR mask; and means for swapping data between physical addresses within the group based on the changed XOR mask. 20. The apparatus of claim 19 , further comprising means for delaying data swaps based on a swap frequency target.

Assignees

Inventors

Classifications

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • by allocating resources to storage systems · CPC title

  • G06F3/0616Primary

    in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

  • using page tables, e.g. page table structures · CPC title

  • Logical to physical mapping or translation of blocks or pages · CPC title

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What does patent US10540100B2 cover?
Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0616. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 21 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).