Photonic crystal all-optical multistep-delay self-or-transformation logic gate

Patent metadata

Field	Value
Publication number	US-10539742-B2
Application number	US-201715626226-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Dec 19, 2014
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A PhC all-optical multistep-delay self-OR-transformation logic gate including an optical switch unit, a PhC structure unit, a reference-light, a memory or delayer, a D-type flip-flop unit and a wave absorbing load; a logic signal X is connected to the input port of a two-branch waveguide whose two output ports are respectively connected with the input port of the memory and the logic-signal input port of the optical switch unit; the output port of the memory is connected with the delay-signal input port of the optical switch unit; the reference-light source is connected with the reference-light input port of the optical switch unit whose three intermediate-signal output ports are respectively connected with the first and second intermediate-signal input ports of the PhC structure unit and the wave absorbing load; and the output port of the PhC structure unit is connected with the D-signal input port of the D-type flip-flop unit.

First claim

What is claimed is:

1. A Photonic Crystal (PhC) all-optical multistep-delay self-OR-transformation logic gate, comprising:
an optical switch unit, a PhC structure unit, a reference-light source, a memory or a delayer, a D-type flip-flop unit and a wave absorbing load; a logic-signal (X) is connected to an input port of first two-branch waveguide, and two output ports of the first two-branch waveguide are respectively connected with an input port of the memory or the delayer and a logic-signal input port of said optical switch unit; an output port of said memory or the delayer is connected with a delay-signal input port of said optical switch unit; a reference-light output (E) from said reference-light source is connected with said reference-light input port of said optical switch unit;
three intermediate-signal output ports of said optical switch unit are respectively connected with a first and second intermediate-signal input ports of said PhC structure unit and said wave absorbing load; a clock-signal (CP) is connected with an input port of second two-branch waveguide, and two output ports of the second two-branch waveguide are respectively connected with a first clock-signal input port of said optical switch unit and a second clock-signal input port of said D-type flip-flop unit;
and a signal-output port of said PhC structure unit is connected with a D signal input port of said D-type flip-flop unit.

2. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 1 , wherein said optical switch unit is a 3×3 optical selector switch, and includes a clock-signal input port, a delay-signal input port, a logic-signal input port, and a reference-light input port and three intermediate-signal output ports.

3. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 1 , wherein said PhC structure unit is a two-dimensional (2D) PhC cross-waveguide nonlinear cavity and is a 2D PhC cross-waveguide four-port network formed by high-refractive-index linear-dielectric pillars, and a left port, lower port, upper port and right port of four-ports correspond to a first intermediate-signal input port, a second intermediate-signal input port, a signal-output port and an idle
port respectively; two mutually-orthogonal quasi-one-dimensional (quasi-1D) PhC structures are placed along longitudinal direction in vertical waveguide and transverse direction in horizontal waveguide, a nonlinear dielectric pillar is arranged in the middle of the cross waveguide, the nonlinear dielectric pillar is made of a nonlinear material, and a cross section of the nonlinear dielectric pillar is square, circular, oval, triangular, or polygonal; a dielectric constant of rectangular high-refractive-index linear-dielectric pillars clinging to the nonlinear dielectric pillar and close to said signal-output port of the PhC-structure unit is equal to that of the nonlinear dielectric pillar under weak light conditions; and said quasi-1D PhC structures and the nonlinear dielectric pillar constitute a waveguide defect cavity.

4. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein said 2D PhC is a (2k+1)*(2k+1) structure, where k is an integer equal to or greater than 3.

5. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein a cross section of the high-refracture-index linear-dielectric pillars of said 2D PhC is circular, oval, triangular, or polygonal.

6. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein a background filling material for the 2D PhC is a low-refractive-index dielectric having a refractive index less than 1.4.

7. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein a background filling material for the 2D PhC is air.

8. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein a cross section of the high-refractive-index linear-dielectric pillar of the cross waveguide is rectangular, polygonal, circular, or oval.

9. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein high-refractive-index linear-dielectric pillar of the cross waveguide has a refractive index of value more than 2.

10. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 3 , wherein high-refractive-index linear-dielectric pillar of the cross waveguide has a refractive index of 3.4.

11. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 1 , wherein said memory or the delayer includes an input port and an output port; the output signal of the memory or the delayer equals an input signal input to the memory before k steps, where k is an integer equal to or greater than 3.

12. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 11 , wherein said memory or the delayer is a k-step delayer.

13. The PhC all-optical multistep-delay self-OR-transformation logic gate in accordance with claim 1 , wherein said D-type flip-flop unit includes a clock-signal input port, a D signal input port and a system output port; and said input signal of said D signal input port is equal to said output signal of the signal-output port of said PhC structure unit.

Assignees

• Ouyang Zhengbiao
• Univ Shenzhen

Inventors

• Ouyang Zhengbiao
• Yu Quanqiang

Classifications

• G02B2006/1213

  comprising photonic band-gap structures or photonic lattices · CPC title

• G02F1/365

  in an optical waveguide structure (G02F1/377, {G02F1/395} take precedence) · CPC title

• G02F3/00 Primary

  Optical logic elements; Optical bistable devices · CPC title

• G02B6/125

  Bends, branchings or intersections · CPC title

• G02F1/3501

  Constructional details or arrangements of non-linear optical devices, e.g. shape of non-linear crystals · CPC title