Analog circuit fault diagnosis method using single testable node

Patent metadata

Field	Value
Publication number	US-10539613-B2
Application number	US-201515555076-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Aug 7, 2015
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) determining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters. The method can convert a single signal into a plurality of signals without losing original measurement information, and extract an independent fault mode feature factor reflecting variations of a circuit structure in different fault modes, can be used to study an associated mode determination rule and successfully complete classification of circuit fault modes.

First claim

What is claimed is:

1. An analog circuit fault diagnosis method using a single testable node, comprising:
(1) obtaining prior sample data vectors under each of fault modes: obtaining M groups of voltage sample vectors V ij of an analog circuit under test under each of the fault modes F i by using computer simulation software, wherein i=1, 2, . . . , N, j=1, 2, 3, . . . , M, N is a total number of the fault modes of the circuit, i represents that the circuit works under a i th fault mode, j is a j th collected sample, and V ij represents a j th voltage sample vector collected when the circuit works under a i th fault mode;
(2) computing a statistical average

V
i

=

∑

j
=
1

M

⁢

V
ij

/
M

of the prior sample data vectors under each of the fault modes, wherein i=1, 2, . . . , N, and V i is voltage sample statistical average vectors when the circuit works under the fault modes F i ;
(3) decomposing a signal by an orthogonal Haar wavelet analysis filter set: decomposing the voltage sample statistical average vectors V i under each of the fault modes into (K+1) filter output signals by a K-layer orthogonal Haar wavelet filter set;
(4) extracting feature factors of prior sample fault modes: extracting (K+1) feature factors s i,d of the prior sample fault modes through processing the (K+1) filter output signals under the fault modes F i by using a blind source processing technology, wherein d represents a serial number of fault feature factors, and d=1, 2, . . . , K+1, and s i,d represents a d th feature factor of the prior sample fault modes of a voltage sample signal under the fault mode F i ;
(5) extracting feature factors of a fault-mode-to-be-tested: collecting M groups of voltage testable vectors of the analog circuit under the fault-mode-to-be-tested, computing a statistical average of the voltage testable vectors, decomposing by the orthogonal Haar wavelet filter set in the step (3), and obtaining (K+1) feature factors s T,h of the voltage testable vectors under the fault-mode-to-be-tested through the blind source processing technology in step (4), wherein T represents to-be-tested, which is the first letter of Test, and is intended to distinguish the fault-mode-to-be-tested and the prior sample fault modes; h represents a serial number of the feature factors, h=1, 2, . . . , K+1, and s T,h represents a h th feature factor of a voltage testable signal under the fault-mode-to-be-tested;
(6) computing a correlation coefficient matrix R i and correlation metric parameters δ i between the feature factors of the fault-mode-to-be-tested and the feature factors of the prior sample fault modes all the fault modes F i ;

R
i

=

[

ρ
11

ρ
12

⋯

ρ

1
⁢

(

K
+
1

)

ρ
21

ρ
22

⋯

ρ

2
⁢

(

K
+
1

)

⋮

⋮

⋮

⋮

ρ

(

K
+
1

)

⁢
1

ρ

(

K
+
1

)

⁢
2

⋯

ρ

(

K
+
1

)

⁢

(

K
+
1

)

]

,

Assignees

• Univ Hefei Technology

Inventors

• He Yigang
• Yuan Lifen
• Wu Lei
• Sun Yesheng
• Zhang Chaolong
• Long Ying
• Cheng Zhen
• Yuan Zhijie
• Zhao Deqin

Classifications

• G01R31/3161 Primary

  Marginal testing · CPC title

• G01R31/316 Primary

  Testing of analog circuits {(G01R31/2851 takes precedence)} · CPC title