Charge pump control circuit

Patent metadata

Field	Value
Publication number	US-10536076-B2
Application number	US-201816127328-A
Country	US
Kind code	B2
Filing date	Sep 11, 2018
Priority date	Jun 7, 2018
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A charge pump control circuit is provided in embodiments of the present disclosure, and the charge pump control circuit includes: a charge pump, having a clock interface; a feedback circuit, configured to sample an output voltage of the charge pump to obtain a sampling voltage; a reference voltage generating circuit, having an output terminal outputting a reference voltage; and a comparator, configured to compare the sampling voltage with the reference voltage; wherein the charge pump control circuit further includes: a logic combination circuit, wherein an input terminal of the logic combination circuit is coupled with an output terminal of the comparator, and the logic combination circuit is configured to generate a clock pulse signal according to a comparison result outputted by the comparator, and the clock pulse signal is transmitted to the clock interface of the charge pump.

First claim

The invention claimed is:

1. A charge pump control circuit, comprising:
a charge pump, having a clock interface;
a feedback circuit, configured to sample an output voltage of the charge pump to obtain a sampling voltage;
a reference voltage generating circuit, having an output terminal outputting a reference voltage; and
a comparator, configured to compare the sampling voltage with the reference voltage;
wherein the charge pump control circuit further comprises:
a logic combination circuit, wherein an input terminal of the logic combination circuit is coupled with an output terminal of the comparator, and the logic combination circuit is configured to generate a clock pulse signal according to a comparison result outputted by the comparator, and the clock pulse signal is transmitted to the clock interface of the charge pump,
wherein the reference voltage generating circuit comprises a protection circuit, and when the output voltage decreases, and the sampling voltage cannot re-follow the reference voltage within one pulse width of the clock pulse signal, the protection circuit releases a charge of the output terminal of the reference voltage generating circuit until the sampling voltage is higher than the reference voltage.

2. The charge pump control circuit according to claim 1 , wherein a positive pole of the comparator is configured to receive the sampling voltage, and a negative pole of the comparator is configured to receive the reference voltage;
wherein the logic combination circuit comprises a clock pulse signal generation module for generating the clock pulse signal, and the clock pulse signal generation module comprises:
a NOT gate, having an input terminal coupled with the output terminal of the comparator;
a delay module; and
a first NOR gate, having a first input terminal coupled with an output terminal of the NOT gate through the delay module, a second input terminal coupled with the output terminal of the comparator, and an output terminal outputting the clock pulse signal.

3. The charge pump control circuit according to claim 1 , wherein a positive pole of the comparator is configured to receive the sampling voltage, and a negative pole of the comparator is configured to receive the reference voltage;
wherein the logic combination circuit comprises a clock pulse signal generation module for generating the clock pulse signal, and the clock pulse signal generation module comprises:
a delay module;
a first NOT gate, having an input terminal coupled with the output terminal of the comparator;
a NAND gate, having a first input terminal coupled with the output terminal of the first NOT gate through the delay module, and a second input terminal coupled with the output terminal of the comparator; and
a second NOT gate, having an input terminal receiving a signal of the output terminal of the NAND gate, and an output terminal outputting the clock pulse signal.

4. The charge pump control circuit according to claim 1 , wherein the reference voltage generating circuit obtains the reference voltage by sampling a voltage of a power supply of the charge pump control circuit.

5. The charge pump control circuit according to claim 4 , wherein the reference voltage generating circuit comprises:
a first resistor, having a first terminal is coupled with a first terminal of a first switch, wherein a second terminal of the first switch is coupled with the power supply;
a second resistor, having a first terminal coupled with a second terminal of the first resistor, and a second terminal grounded;
a first capacitor, having a first plate coupled with the power supply; and
a second capacitor, having a first plate coupled with the first plate of the first capacitor and a first terminal of a second switch, and a second plate grounded, wherein a second terminal of the second switch is coupled with the first terminal of the second resistor;
wherein control terminals of the first switch and the second switch are configured to receive a control signal outputted by a controller which is configured to generate the control signal according to the comparison result outputted by the comparator.

6. The charge pump control circuit according to claim 5 , wherein the reference voltage generating circuit further comprises: a third capacitor, having a first plate coupled with the first terminal of the second resistor, and a second plate grounded.

7. The charge pump control circuit according to claim 1 , wherein the feedback circuit comprises:
a third resistor, having a first terminal coupled with a first terminal of a third switch, wherein a second terminal of the third switch is coupled with an output terminal of the charge pump;
a fourth resistor, having a first terminal coupled with a second terminal of the third resistor, and a second terminal grounded;
a fourth capacitor, having a first plate coupled with the output terminal of the charge pump, a second plate coupled with a first terminal of a fourth switch, wherein a second terminal of the fourth switch is coupled with the first terminal of the fourth resistor; and
a fifth capacitor, having a first plate coupled with the second plate of the fourth capacitor, and a second plate grounded;
wherein control terminals of the third switch and the fourth switch are configured to receive a control signal outputted by a controller, which is configured to generate the control signal according to the comparison result outputted by the comparator.

8. The charge pump control circuit according to claim 1 , wherein the protection circuit comprises a switch transistor and a fifth switch, wherein a drain of the switch transistor is coupled with a first terminal of the fifth switch, a second terminal of the fifth switch is coupled with the output terminal of the reference voltage generating circuit, a source of the switch transistor is grounded, and a gate of the switch transistor is coupled with a predetermined bias voltage; and
wherein the logic combination circuit comprises a switch control signal generating module, wherein the switch control signal generating module is configured to generate a switch control signal according to the comparison result outputted by the comparator and the clock pulse signal, and a control terminal of the fifth switch is configured to receive the switch control signal.

9. The charge pump control circuit according to claim 8 , wherein the switch control signal generating module comprises a second NOR gate, wherein the second NOR gate has a first input terminal receiving an output signal outputted by the comparator, a second input terminal receiving the clock pulse signal, and an output terminal outputting the switch control signal.

Assignees

• Shanghai Huahong Grace Semiconductor Mfg Corp

Inventors

• Zhu Wenyi
• Xiao Jun

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/0041

  Control circuits in which a clock signal is selectively enabled or disabled · CPC title

• H02M1/0006

  Arrangements for supplying an adequate voltage to the control circuit of converters · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title