Resistance change memory device

Patent metadata

Field	Value
Publication number	US-10535818-B2
Application number	US-201815942236-A
Country	US
Kind code	B2
Filing date	Mar 30, 2018
Priority date	Jul 7, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A resistance change memory device is provided. The resistance change memory device includes a lower electrode, a tunneling barrier layer disposed on the lower electrode, a resistance switching layer disposed on the tunneling barrier layer, an oxygen vacancy reservoir layer disposed on the resistance switching layer, and an upper electrode disposed on the oxygen vacancy reservoir layer. The oxygen vacancy reservoir layer is electrically conductive.

First claim

What is claimed is:

1. A resistance change memory device, comprising:
a lower electrode;
a tunneling barrier layer disposed on the lower electrode;
a resistance switching layer disposed on the tunneling barrier layer;
an oxygen vacancy reservoir layer disposed directly on the resistance switching layer, the oxygen vacancy reservoir layer being electrically conductive;
an upper electrode disposed on the oxygen vacancy reservoir layer; and
a conductive filament disposed in the resistance switching layer,
wherein the oxygen vacancy reservoir layer comprises a metal oxide that contains a stoichiometrically deficient amount of oxygen atoms.

2. The resistance change memory device of claim 1 ,
wherein the tunneling barrier layer comprises an insulating metal oxide that satisfies a stoichiometric ratio.

3. The resistance change memory device of claim 1 ,
wherein an oxygen vacancy concentration of the resistance switching layer is higher than an oxygen vacancy concentration of the tunneling barrier layer.

4. The resistance change memory device of claim 1 , wherein the metal oxide of the oxygen vacancy reservoir layer comprises one or more of titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, and iron oxide.

5. The resistance change memory device of claim 1 ,
wherein the resistance switching layer comprises one or more elements in the tunneling barrier layer and one or more elements in the oxygen vacancy reservoir layer.

6. The resistance change memory device of claim 1 ,
wherein the conductive filament comprises oxygen vacancies.

7. The resistance change memory device of claim 1 ,
wherein the resistance change memory device is written with a first resistance state when the conductive filament connects the tunneling barrier layer and the oxygen vacancy reservoir layer to each other, and
wherein the resistance change memory device is written with a second resistance state when the conductive filament is in a disconnected state between the tunneling barrier layer and the oxygen vacancy reservoir layer.

8. The resistance change memory device of claim 1 , further comprising:
a parasitic filament disposed in the tunneling barrier layer.

9. The resistance change memory device of claim 8 ,
wherein the conductive filament and the parasitic filament are disconnected from each other.

10. The resistance change memory device of claim 1 , wherein the resistance switching layer is disposed directly on the tunneling barrier layer.

11. A resistance change memory device comprising:
a lower electrode;
a first metal oxide layer disposed on the lower electrode, the first metal oxide layer being electrically insulative;
a second metal oxide layer directly disposed on the first metal oxide layer, the second metal oxide layer comprising a conductive filament;
a third metal oxide layer disposed on the second metal oxide layer, the third metal oxide layer being electrically conductive; and
an upper electrode disposed on the third metal oxide layer,
wherein the third metal oxide layer comprises a metal oxide material that contains a stoichiometrically deficient amount of oxygen atoms.

12. The resistance change memory device of claim 11 ,
wherein an oxidation potential of a material in the first metal oxide layer is higher than an oxidation potential of a material in the second metal oxide layer.

13. The resistance change memory device of claim 11 ,
wherein the resistance change memory device is written with a first resistance state when the conductive filament connects the first metal oxide layer and the third metal oxide layer to each other, and
wherein the resistance change memory device is written with a second resistance state when the conductive filament is in a disconnected state between the first metal oxide layer and the third metal oxide layer.

14. The resistance change memory device of claim 11 ,
wherein the first metal oxide layer comprises a metal oxide material that satisfies a stoichiometric ratio; and
wherein the second metal oxide layer comprises a metal oxide material that contains a stoichiometrically deficient amount of oxygen atoms.

15. The resistance change memory device of claim 14 ,
wherein the first metal oxide layer comprises one or more of titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, and iron oxide.

16. The resistance change memory device of claim 14 ,
wherein the third metal oxide layer comprises a metal oxide material having oxygen vacancies, and
wherein the metal oxide material comprises one or more of titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, and iron oxide.

17. The resistance change memory device of claim 11 ,
wherein the second metal oxide layer comprises one or more elements in the first metal oxide layer and one or more elements in the third oxide layer.

18. The resistance change memory device of claim 11 , further comprising a parasitic filament disposed in the first metal oxide layer,
wherein the parasitic filament is disconnected from the conductive filament.

19. The resistance change memory device of claim 11 ,
wherein the first metal oxide layer comprises a tunneling barrier layer.

Assignees

• Sk Hynix Inc

Inventors

• Ha Tae Jung

Classifications

• G11C2013/009

  Write using potential difference applied between cell electrodes · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2213/51

  Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title