Field-effect transistor, method of manufacturing the same, and radio-frequency device

Patent metadata

Field	Value
Publication number	US-10535607-B2
Application number	US-201816050815-A
Country	US
Kind code	B2
Filing date	Jul 31, 2018
Priority date	Apr 18, 2014
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

First claim

The invention claimed is:

1. A field-effect transistor comprising:
a gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode in between;
contact plugs comprising a first conductive material, wherein a first contact plug of the contact plugs is provided on the source region, and wherein a second contact plug of the contact plugs is provided on the drain region;
first metals comprising a second conductive material that is different than the first conductive material, wherein one of the first metals is stacked on the first contact plug, and wherein a second one of the first metals is stacked on the second contact plug;
one or more insulating films provided (1) between the contact plugs along an in-plane direction of the semiconductor layer and (2) below bottom surfaces of the first metals along a stacking direction, wherein the one or more insulating films comprise
a first portion of the one or more insulating films provided between the contact plugs along the in-plane direction of the semiconductor layer and below the bottom surfaces of the first metals along the stacking direction, and the first portion of the one or more insulating films occupy a region between the first contact plug and a side surface of the gate electrode; and
a second portion of the one or more insulating films provided between the contact plugs along the in-plane direction of the semiconductor layer and above a first portion of a top surface of the gate electrode; and
a low-dielectric constant region provided in a region over a second portion of the top surface of the gate electrode, between the contact plugs along the in-plane direction of the semiconductor layer, and provided at least in a first region below the bottom surfaces of the first metals along the stacking direction.

2. The field-effect transistor according to claim 1 , wherein the low-dielectric constant region comprises a cavity.

3. The field-effect transistor according to claim 2 , wherein a top section of the cavity is formed by the second portion of the one or more insulating films.

4. The field-effect transistor according to claim 2 , wherein a top section of the cavity is formed by the second portion of the one or more insulating films below or at the bottom surfaces of the first metals along the stacking direction.

5. The field-effect transistor according to claim 2 , wherein one of the second portion of the one or more insulating films is provided in a second region between the bottom surfaces of the first metals and the top surface of the gate electrode, along the stacking direction, so as to form a top section of the cavity.

6. The field-effect transistor according to claim 2 , wherein the one or more insulating films include
a first insulating film at least extending along the side surface of the gate electrode,
a second insulating film, at least a portion of the first insulating film provided between the second insulating film and the gate electrode, and
a third insulating film provided between the contact plugs along the in-plane direction, and provided below the bottom surfaces of the first metals along the stacking direction, the third insulating film positioned outside a side section of the cavity.

7. The field-effect transistor according to claim 6 , wherein the one or more insulating films further include a fourth insulating film above a top surface of the third insulating film, and wherein a top section of the cavity is below the fourth insulating film.

8. The field-effect transistor according to claim 7 , wherein at least one of the first insulating film, the second insulating film, the third insulating film and the fourth insulating film is provided between the cavity and the gate electrode.

9. The field-effect transistor according to claim 7 , wherein, as viewed in a cross section including the stacking direction and a direction from the source region to the drain region, the cavity on the gate electrode is a single cavity.

10. The field-effect transistor according to claim 7 , wherein the second insulating film at least extending along the side surface of the gate electrode.

11. The field-effect transistor according to claim 7 , wherein the second portion of the one or more insulating films include the fourth insulating film.

12. The field-effect transistor according to claim 7 , wherein the top surface of the third insulating film has a recess above the top surface of the gate electrode,
the cavity is provided at least in a part of the recess,
the fourth insulating film covers a bottom surface of the recess and a side surface of the recess,
a first thickness of the fourth insulating film between the cavity and the bottom surface of the recess is smaller than a second thickness of the fourth insulating film between the cavity and the side surface of the recess,
a width of the cavity is smaller than a width of a top region of the recess,
the width of the top region of the recess is smaller than a width of the region of the top surface of the gate electrode,
the bottom surface of the recess consists of Si and N,
the second insulating film at least extends along the side surface of the gate electrode, and as viewed in a cross section including the stacking direction and a direction from the source region to the drain region, the cavity on the gate electrode is a single cavity.

13. The field-effect transistor according to claim 7 , further comprising
an active region including
the gate electrode,
the semiconductor layer,
the contact plugs and
an isolation region provided outside the active region, the isolation region including a gate contact coupled to the gate electrode.

14. The field-effect transistor according to claim 13 , wherein the gate electrode extends along one direction, and the contact plugs, the first metals, and the cavity extends in parallel with the gate electrode.

15. The field-effect transistor according to claim 7 , wherein the top surface of the third insulating film has a recess above the top surface of the gate electrode.

16. The field-effect transistor according to claim 15 , wherein the cavity is provided at least in a part of the recess.

17. The field-effect transistor according to claim 16 , wherein the fourth insulating film covers a bottom surface of the recess and a side surface of the recess.

18. The field-effect transistor according to claim 17 , wherein a first thickness of the fourth insulating film between the cavity and the bottom surface of the recess is smaller than a second thickness of the fourth insulating film between the cavity and the side surface of the recess.

19. The field-effect transistor according to claim 16 , wherein a width of the cavity is smaller than a width of a top region of the recess.

20. The field-effect transistor according to claim 19 , wherein the width of the top region of the recess is smaller than a width of the region of the top surface of the gate electrode.

21. The field-effect transistor according to claim 19 , wherein at least one of the first insulating film, the second insulating film, the third insulating film and the fourth insulating film is provided between the cavity and the gate electrode.

22. The field-effect transistor according to claim 19 , wherein the second insulating film at least extending along the side surface of the gate electrode.

23. The field-effect transistor according to claim 19 , wherein, as viewed in a cross section including the stack

Assignees

• Sony Corp

Inventors

• Saka Naoki
• Okamoto Daisaku
• Tanaka Hideki

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/484 Primary

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title