Configuring dynamic random access memory refreshes for systems having multiple ranks of memory

Patent metadata

Field	Value
Publication number	US-10535393-B1
Application number	US-201816041778-A
Country	US
Kind code	B1
Filing date	Jul 21, 2018
Priority date	Jul 21, 2018
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

First claim

What is claimed is:

1. An electronic device, comprising:
a memory functional block that includes multiple ranks of memory; and
a memory controller functional block coupled to the memory, the memory controller including refresh logic that is configured to:
detect, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval;
based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, determine a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval, wherein each rank of memory is included at a respective place in the refresh order relative to other ranks of memory from the two or more ranks of memory based at least in part on the one or more properties of the buffered memory accesses; and
perform, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

2. The electronic device of claim 1 , wherein, when performing, in the refresh order, the refreshes for the two or more ranks of memory during the refresh interval, the refresh logic is configured to:
for a given rank of memory of the two or more ranks of memory that is first in the refresh order, pause corresponding buffered memory accesses and performing the refresh for the given rank of memory substantially immediately upon the commencement of the refresh interval.

3. The electronic device of claim 1 , wherein when performing, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval, the refresh logic is configured to:
while a refresh is performed for a preceding rank of memory of the ranks of memory in the refresh order, performing corresponding buffered memory accesses for a given rank of memory of the ranks of memory, thereby preparing the given rank of memory for a subsequent refresh.

4. The electronic device of claim 3 , wherein the refresh logic is further configured to:
while the refresh is performed for the preceding rank of memory of the ranks of memory in the refresh order, pause sending specified memory commands to the given rank of memory, thereby preparing the given rank of memory for the subsequent refresh.

5. The electronic device of claim 1 , wherein the refresh logic is further configured to:
dividing the refresh interval into a number of sub-intervals based at least in part on a number of the ranks of memory for which a refresh is to be performed during the refresh interval, wherein a refresh is to be performed for a different one of the two or more ranks of memory during each sub-interval.

6. The electronic device of claim 1 , wherein:
the properties of the buffered memory accesses comprise a count of the buffered memory accesses; and
a rank of memory having more buffered memory accesses is included later in the refresh order than a rank of memory having fewer buffered memory accesses.

7. The electronic device of claim 1 , wherein:
the properties of the buffered memory accesses comprise a type of each of the memory accesses; and
a rank of memory having more of a given type of buffered memory accesses is included earlier in the refresh order than a rank of memory having fewer of the given type of buffered memory accesses.

8. The electronic device of claim 7 , wherein the type of each of the memory accesses includes one of a memory read or a memory write.

9. The electronic device of claim 1 , wherein:
the properties of the buffered memory accesses comprise a priority of the memory accesses; and
a rank of memory having more higher-priority buffered memory accesses is included earlier in the refresh order than a rank of memory having fewer higher-priority buffered memory accesses.

10. The electronic device of claim 1 , wherein the refresh logic is further configured to:
based on, in addition to the one or more properties of the buffered memory accesses, operations performed or to be performed by the memory controller, determine a refresh order for performing refreshes during the refresh interval for the at least one of the ranks of memory.

11. The electronic device of claim 1 , wherein a refresh is to be performed for a given rank of memory when a specified number of memory accesses are buffered in the given rank of memory.

12. The electronic device of claim 1 , wherein:
each rank includes one or more banks of memory; and
the detecting, determining, and performing operations are performed at the resolution of banks of memory within the ranks of memory, so that only a portion of the one or more banks of memory in a given rank of memory may be refreshed during the refresh interval.

13. A method for operating an electronic device having a memory functional block that includes multiple ranks of memory and a memory controller functional block that includes refresh logic, the method comprising:
detecting, by the refresh logic, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval;
based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, determining, by the refresh logic, a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval, wherein each rank of memory is included at a respective place in the refresh order relative to other ranks of memory from the two or more ranks of memory based at least in part on the one or more properties of the buffered memory accesses; and
performing, by the memory controller, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

14. The method of claim 13 , wherein performing, in the refresh order, the refreshes for the two or more ranks of memory during the refresh interval comprises:
for a given rank of memory of the two or more ranks of memory that is first in the refresh order, pausing corresponding buffered memory accesses and performing the refresh for the given rank of memory substantially immediately upon the commencement of the refresh interval.

15. The method of claim 13 , wherein performing, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval comprises:
while a refresh is performed for a preceding rank of memory of the ranks of memory in the refresh order, performing corresponding buffered memory accesses for a given rank of memory of the ranks of memory, thereby preparing the given rank of memory for a subsequent refresh.

16. The method of claim 15 , further comprising:
while the refresh is performed for the preceding rank of memory of the ranks of memory in the refresh order, pausing sending specified memory commands to the given rank of memory, thereby preparing the given rank of memory for the subsequent refresh.

17. The method of claim 13 , further comprising:
dividing the refresh interval into a number of sub-intervals based at least in part on a number of the ranks of memory for which a refresh is to be performed during the refresh interval, wherein a refresh is to be performed for one of the two or more ranks of memory during each sub-interval.

18. The method of claim 13 , wherein:
the properties of the buffered memory accesses comprise a count of the buffered memory accesses; and
a rank of memory having more buffered memory accesses is included later in the refresh order than a rank of memory having fewer buffere

Assignees

• Advanced Micro Devices Inc

Inventors

• Balakrishnan Kedarnath

Classifications

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40603

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C11/409

  Read-write [R-W] circuits · CPC title