Magnetoresistive devices and methods therefor

Patent metadata

Field	Value
Publication number	US-10535390-B2
Application number	US-201715831736-A
Country	US
Kind code	B2
Filing date	Dec 5, 2017
Priority date	Dec 6, 2016
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.

First claim

What is claimed is:

1. A method of manufacturing a magnetoresistive device, comprising:
(a) forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device, and wherein the one or more regions of the magnetoresistive stack includes a fixed region, a free region, and a dielectric region disposed between the fixed region and the free region;
(b) patterning or etching at least a portion of the magnetoresistive stack;
(c) performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon after step (b), wherein the sole annealing process is performed at a first temperature between about 400-500° C. and is a combined annealing step configured to anneal both the at least one electronic device and the one or more regions formed on the substrate, and wherein the sole annealing process is performed after patterning or etching the free region and before patterning or etching the dielectric region; and
(d) subsequent to step (c), performing all additional processing on the substrate at a second temperature below the first temperature.

2. The method of claim 1 , wherein the at least one electronic device is a transistor.

3. The method of claim 1 , wherein patterning or etching at least a portion of the magnetoresistive stack includes patterning or etching the fixed region.

4. The method of claim 1 , wherein the at least one electronic device in the substrate is not annealed prior to performing the sole annealing process.

5. The method of claim 1 , wherein performing the sole annealing process includes exposing the substrate with the one or more magnetoresistive regions formed thereon to a pressure between about 1-6 atmospheres.

6. A method of manufacturing a magnetoresistive device, comprising:
forming multiple regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device;
patterning or etching a first portion of the magnetoresistive stack;
subsequent to the step of patterning or etching the first portion of the magnetoresistive stack, performing an annealing process on the substrate having the magnetoresistive stack formed thereon, wherein the annealing process is performed after patterning or etching some of the multiple regions of the magnetoresistive stack and before patterning or etching all of the multiple regions of the magnetoresistive stack, wherein the annealing process is performed at a first temperature between about 400-500° C. and is a combined annealing step configured to anneal both the at least one electronic device and the one or more regions formed on the substrate;
subsequent to the annealing process, patterning or etching a second portion of the magnetoresistive stack; and
performing all additional processing on the substrate at a second temperature below the first temperature.

7. The method of claim 6 , wherein the at least one electronic device is a transistor.

8. The method of claim 6 , wherein the multiple regions of the magnetoresistive stack includes a fixed region, a free region, and an intermediate region disposed between the fixed region and the free region, and wherein (a) patterning or etching the first portion includes patterning or etching regions of the magnetoresistive stack above the intermediate region, and (b) patterning or etching the second portion includes patterning or etching regions of the magnetoresistive stack below the first portion.

9. The method of claim 6 , wherein the multiple regions of the magnetoresistive stack includes a fixed region, a free region, and a dielectric region disposed between the fixed region and the free region, and wherein the first portion includes at least the fixed region, the free region, and the dielectric region, and the second portion incudes regions of the magnetoresistive stack below the first portion.

10. The method of claim 6 , wherein the magnetoresistive stack is a magnetic tunnel junction.

11. The method of claim 6 , wherein the multiple regions of the magnetoresistive stack includes a fixed region, a free region, and a dielectric region disposed between the fixed region and the free region, and wherein patterning or etching the first portion includes patterning or etching at least the fixed region.

12. The method of claim 6 , wherein the annealing process is performed at a pressure between about 1-6 atmospheres.

13. The method of claim 6 , wherein the at least one electronic device on the substrate is not annealed prior to performing the annealing process.

14. A method of manufacturing a magnetoresistive device, comprising:
forming a magnetoresistive stack on a substrate, wherein the magnetoresistive stack includes multiple layers formed on the substrate and wherein the substrate includes one or more transistors;
after forming the magnetoresistive stack, performing a combined annealing process, wherein the combined annealing process anneals both the one or more transistors and the magnetoresistive stack, and wherein the combined annealing process is performed at a temperature between about 400-500° C. and a pressure between about 1-6 atmospheres;
patterning or etching at least a portion of the magnetoresistive stack, wherein the combined annealing process is performed after patterning or etching some of the multiple layers and before patterning or etching all of the multiple layers; and
performing all additional processing on the substrate at a temperature below a maximum temperature of the combined annealing process.

15. The method of claim 14 , wherein the one or more transistors on the substrate is not annealed prior to performing the combined annealing process.

16. The method of claim 14 , wherein the combined annealing process is performed during the step of patterning or etching the magnetoresistive stack.

17. The method of claim 14 , wherein the magnetoresistive stack includes a fixed region, a free region, and a dielectric region disposed between the fixed region and the free region, and wherein the combined annealing process is performed after patterning or etching at least a portion of one or more of the fixed region, the free region, and the dielectric region.

Assignees

• Everspin Technologies Inc

Inventors

• Aggarwal Sanjeev
• Deshpande Sarin A
• Slaughter Jon

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/226

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic