Shader writes to compressed resources

Patent metadata

Field	Value
Publication number	US-10535178-B2
Application number	US-201615389075-A
Country	US
Kind code	B2
Filing date	Dec 22, 2016
Priority date	Dec 22, 2016
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Systems, apparatuses, and methods for performing shader writes to compressed surfaces are disclosed. In one embodiment, a processor includes at least a memory and one or more shader units. In one embodiment, a shader unit of the processor is configured to receive a write request targeted to a compressed surface. The shader unit is configured to identify a first block of the compressed surface targeted by the write request. Responsive to determining the data of the write request targets less than the entirety of the first block, the first shader unit reads the first block from the cache and decompress the first block. Next, the first shader unit merges the data of the write request with the decompressed first block. Then, the shader unit compresses the merged data and writes the merged data to the cache.

First claim

What is claimed is:

1. A processor comprising:
a cache; and
one or more shader units coupled to the cache;
wherein responsive to a write request targeting a compressed surface, a shader unit of the one or more shader units is configured to:
identify a first block of the compressed surface targeted by the write request;
responsive to detecting all data of the first block is set to a single value:
prevent logic for fetching and decompressing the first block from being activated;
compress data of the write request to form a second block; and
write the second block to the cache without fetching or decompressing the first block.

2. The processor as recited in claim 1 , wherein responsive to detecting that all the data of the first block is set to the single value, the shader unit is configured to merge the data of the write request with the data of the single value prior to compressing the merged data and forming the second block.

3. The processor as recited in claim 1 , wherein responsive to determining that the data of the write request updates an entirety of the first block, the shader unit is further configured to overwrite the first block in the cache with the second block.

4. The processor as recited in claim 1 , wherein responsive to detecting a second condition, the shader unit is configured to:
activate logic for fetching and decompressing a third block;
merge data of a second write request with the decompressed third block to form a fourth block; and
compress and write the fourth block to the cache.

5. The processor as recited in claim 4 , wherein the second condition is determining that the data of the second write request targets less than an entirety of the third block.

6. The processor as recited in claim 5 , wherein the shader unit is further configured to access metadata associated with the third block, wherein the metadata includes information specifying a type of compression used to compress the third block.

7. The processor as recited in claim 6 , wherein the shader unit is further configured to utilize the information to decompress the third block.

8. A method for use in a computing device, the method comprising:
receiving a write request targeting a compressed surface;
identifying, by a shader unit, a first block of the compressed surface targeted by the write request;
responsive to determining all data of the first block is set to a single value:
preventing, by the shader unit, logic for fetching and decompressing the first block from being activated;
compressing, by the shader unit, data of the write request to form a second block; and
writing, by the shader unit, the second block to a cache without fetching or decompressing the first block.

9. The method as recited in claim 8 , wherein responsive to determining that all the data of the first block is set to the single value, the method further comprising merging the data of the write request with the data of the single value prior to compressing the merged data and forming the second block.

10. The method as recited in claim 8 , wherein responsive to determining that the data of the write request updates an entirety of the first block, the method further comprising overwriting the first block in the cache with the second block.

11. The method as recited in claim 8 , wherein responsive to detecting a second condition, the method further comprising:
activating logic for fetching and decompressing a third block;
merging data of a second write request with the decompressed third block to form a fourth block; and
compressing and writing the fourth block to the cache.

12. The method as recited in claim 11 , wherein the second condition is determining that the data of the second write request targets less than an entirety of the third block.

13. The method as recited in claim 12 , further comprising accessing metadata associated with the third block, wherein the metadata includes information specifying a type of compression used to compress the third block.

14. The method as recited in claim 13 , further comprising utilizing the information to decompress the third block.

15. A system comprising:
a memory; and
a processor coupled to the memory, wherein the processor comprises one or more shader units;
wherein responsive to a write request targeting a compressed surface, a shader unit of the one or more shader units is configured to:
identify a first block of the compressed surface targeted by the write request;
responsive to detecting all data of the first block is set to a single value:
prevent logic for fetching and decompressing the first block from being activated;
compress data of the write request to form a second block; and
write the second block to the memory without fetching or decompressing the first block.

16. The system as recited in claim 15 , wherein responsive to detecting that all the data of the first block is set to the single value, the shader unit is configured to merge the data of the write request with the data of the single value prior to compressing the merged data and forming the second block.

17. The system as recited in claim 15 , wherein responsive to determining that the data of the write request updates an entirety of the first block, the shader unit is further configured to overwrite the first block in the memory with the second block.

18. The system as recited in claim 15 , wherein responsive to detecting a second condition, the shader unit is configured to:
activate logic for fetching and decompressing a third block;
merge data of a second write request with the decompressed third block to form a fourth block; and
compress and write the fourth block to the memory.

19. The system as recited in claim 18 , wherein the second condition is determining that the data of the second write request targets less than an entirety of the third block.

20. The system as recited in claim 19 , wherein the shader unit is further configured to access metadata associated with the third block, wherein the metadata includes information specifying a type of compression used to compress the third block.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Mirza Jimshed
• Brennan Christopher J
• Chan Anthony
• Lai Leon

Classifications

• G06F2212/401

  Compressed data · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06T15/04

  Texture mapping · CPC title

• G06T15/80

  Shading · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title