Controlling multi-pass rendering sequences in a cache tiling architecture

Patent metadata

Field	Value
Publication number	US-10535114-B2
Application number	US-201514829617-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Aug 18, 2015
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

In one embodiment of the present invention a driver configures a graphics pipeline implemented in a cache tiling architecture to perform dynamically-defined multi-pass rendering sequences. In operation, based on sequence-specific configuration data, the driver determines an optimized tile size and, for each pixel in each pass, the set of pixels in each previous pass that influence the processing of the pixel. The driver then configures the graphics pipeline to perform per-tile rendering operations in a region that is translated by a pass-specific offset backward—vertically and/or horizontally—along a tiled caching traversal line. Notably, the offset ensures that the required pixel data from previous passes is available. The driver further configures the graphics pipeline to store the rendered data in cache lines. Advantageously, the disclosed approach exploits the efficiencies inherent in cache tiling architecture while honoring highly configurable data dependencies between passes in multi-pass rendering sequences.

First claim

The invention claimed is:

1. A computer-implemented method for performing a multi-pass rendering sequence in a tile-based architecture, the method comprising:
calculating a tile size for a current pass through a graphics processing pipeline based at least on algorithmic dependencies between the current pass and one or more previous passes through the graphics processing pipeline, wherein a given generation region is processed by the graphics processing pipeline in each pass;
calculating a set of first generation offsets for the current pass based on a first subset of the algorithmic dependencies;
determining a first generation region for the current pass based on the tile size and the set of first generation offsets; and
processing the first generation region for the current pass by:
configuring the graphics processing pipeline to generate first graphics data for a first set of pixels included in the first generation region, and
configuring the graphics processing pipeline to store the first graphics data in a first set of cache lines included in a cache memory.

2. The computer-implemented method of claim 1 , further comprising:
calculating a set of first invalidation offsets for the current pass based on a second subset of the algorithmic dependencies;
determining a first invalidation region for the current pass based on the first generation region and the set of first invalidation offsets; and
configuring the graphics processing pipeline to invalidate a second set of cache lines that are associated with the first invalidation region and included in the cache memory.

3. The computer-implemented method of claim 2 , further comprising:
configuring the graphics processing pipeline to partition a screen space into a plurality of tiles based on the tile size for the current pass,
wherein a first default region is associated with a first tile; and
wherein determining the first invalidation region for the current pass comprises offsetting the first default region in a backward direction with respect to a traversal line based on the set of first invalidation offsets for the current pass.

4. The computer-implemented method of claim 1 , further comprising:
configuring the graphics processing pipeline to partition a screen space into a plurality of tiles based on the tile size for the current pass,
wherein a first default region is associated with a first tile; and
wherein determining the first generation region for the current pass comprises offsetting the first default region in a backward direction with respect to a traversal line based on the set of first generation offsets for the current pass.

5. The computer-implemented method of claim 1 , wherein the algorithmic dependencies comprise a first mapping between pixels processed during a first pass and pixels processed during a second pass, wherein at least one of the first pass and the second pass are included in the one or more previous passes.

6. The computer-implemented method of claim 5 , wherein the algorithmic dependencies further comprise a second mapping between the pixels processed during the second pass and pixels processed during a third pass of the graphics processing pipeline.

7. The computer-implemented method of claim 6 , wherein the first mapping is different than the second mapping.

8. The computer-implemented method of claim 6 , wherein the algorithmic dependencies further comprise a third mapping between the pixels processed during the first pass and the pixels processed during the third pass.

9. One or more non-transitory, computer-readable storage media including instructions that, when executed by one or more processors, cause the one or more processors to perform a multi-pass rendering sequence in a tile-based architecture, by performing the steps of:
calculating a tile size for a current pass through a graphics processing pipeline based at least on algorithmic dependencies between the current pass and one or more previous passes through the graphics processing pipeline, wherein a given generation region is processed by the graphics processing pipeline in each pass;
calculating a set of first generation offsets for the current pass based on a first subset of the algorithmic dependencies;
determining a first generation region for the current pass based on the tile size and the set of first generation offsets; and
processing the first generation region for the current pass by:
configuring the graphics processing pipeline to generate first graphics data for a first set of pixels included in the first generation region, and
configuring the graphics processing pipeline to store the first graphics data in a first set of cache lines included in a cache memory.

10. The one or more non-transitory, computer-readable storage media of claim 9 , further including instructions that, when executed by the one or more processors, cause the one or more processors to further perform the steps of:
calculating a set of first invalidation offsets for the current pass based on a second subset of the algorithmic dependencies;
determining a first invalidation region for the current pass based on the first generation region and the set of first invalidation offsets; and
configuring the graphics processing pipeline to invalidate a second set of cache lines that are associated with the first invalidation region and included in the cache memory.

11. The one or more non-transitory, computer-readable storage media of claim 10 , further including instructions that, when executed by the one or more processors, cause the one or more processors to further perform the step of:
configuring the graphics processing pipeline to partition a screen space into a plurality of tiles based on the tile size for the current pass,
wherein a first default region is associated with a first tile; and
wherein determining the first invalidation region for the current pass comprises offsetting the first default region in a backward direction with respect to a traversal line based on the set of first invalidation offsets for the current pass.

12. The one or more non-transitory, computer-readable storage media of claim 9 , further including instructions that, when executed by the one or more processors, cause the one or more processors to further perform the step of:
configuring the graphics processing pipeline to partition a screen space into a plurality of tiles based on the tile size for the current pass,
wherein a first default region is associated with a first tile; and
wherein determining the first generation region for the current pass comprises offsetting the first default region in a backward direction with respect to a traversal line based on the set of first generation offsets for the current pass.

13. The one or more non-transitory, computer-readable storage media of claim 12 , wherein the set of first generation offsets for the current pass comprises:
a horizontal offset; and
a vertical offset that is not equal to the horizontal offset.

14. The one or more non-transitory, computer-readable storage media of claim 12 , wherein the set of first generation offsets for the current pass comprises at least one of:
a first filter width; and
a first filter height.

15. The one or more non-transitory, computer-readable storage media of claim 9 , wherein the algorithmic dependencies comprise a first mapping between pixels processed during a first pass and pixels processed during a second pass, wherein at least one of the first pass and the second pass are included in the one or more previous passes.

16. The one or more non-transitory, co

Assignees

• Nvidia Corp

Inventors

• Bolz Jeffrey A

Classifications

• G09G5/14

  Display of multiple viewports · CPC title

• G09G5/363

  Graphics controllers · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title