Methods for CMOS-MEMS integrated devices with multiple sealed cavities maintained at various pressures

US10532926B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10532926-B2
Application numberUS-201615358956-A
CountryUS
Kind codeB2
Filing dateNov 22, 2016
Priority dateJun 27, 2011
Publication dateJan 14, 2020
Grant dateJan 14, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A Microelectromechanical systems (MEMS) structure comprises a MEMS wafer. A MEMS wafer includes a handle wafer with cavities bonded to a device wafer through a dielectric layer disposed between the handle and device wafers. The MEMS wafer also includes a moveable portion of the device wafer suspended over a cavity in the handle wafer. Four methods are described to create two or more enclosures having multiple gas pressure or compositions on a single substrate including, each enclosure containing a moveable portion. The methods include: A. Forming a secondary sealed enclosure, B. Creating multiple ambient enclosures during wafer bonding, C. Creating and breaching an internal gas reservoir, and D. Forming and subsequently sealing a controlled leak/breach into the enclosure.

First claim

Opening claim text (preview).

What is claimed is: 1. A Microelectromechanical Systems (MEMS) structure comprising: a MEMS substrate bonded to a second substrate, forming a plurality of enclosures of at least two types, wherein each of the plurality of enclosures is defined by the MEMS substrate, the second substrate, and a seal-ring between the MEMS substrate and the second substrate, wherein a first enclosure type has a first seal-ring type, wherein a second enclosure type has a second seal-ring type, and wherein the second enclosure type comprises a gap of the seal-ring of the second seal-ring type configured to allow a pressure differential between first enclosure type and the second enclosure type upon sealing the second enclosure type. 2. The MEMS structure of claim 1 , wherein the gap is defined by a predetermined separation of the second seal-ring type in a plane substantially parallel to the MEMS substrate. 3. The MEMS structure of claim 1 , wherein the gap is defined by a difference in thickness of the first seal-ring type relative to the second seal-ring type and the second substrate, wherein the gap lies in a plane substantially orthogonal to the MEMS substrate. 4. The MEMS structure of claim 1 , wherein the gap is defined by a dielectric layer between a MEMS device wafer and a MEMS handle wafer of the MEMS substrate. 5. The MEMS structure of claim 1 , wherein the first enclosure type is sealed with the first seal-ring at a first pressure, at a first temperature, and at a first force applied to the MEMS substrate and the second substrate. 6. The MEMS structure of claim 1 , wherein the second enclosure type is sealed with the second seal-ring type at a second pressure, at a second temperature, and at a second force applied to the MEMS substrate and the second substrate. 7. The MEMS structure of claim 6 , wherein at least one of the second temperature or the second force applied is at a predetermined value to seal the gap in the second enclosure type. 8. The MEMS structure of claim 1 , wherein the second substrate comprises a complementary metal-oxide semiconductor (CMOS) substrate. 9. The MEMS structure of claim 1 , wherein at least one of the first seal-ring type or the second seal-ring type comprises solder. 10. A method, comprising: forming a Microelectromechanical Systems (MEMS) substrate with cavities; contacting the MEMS substrate with a second substrate, thereby forming a plurality of enclosures of at least two types, wherein each of the plurality of enclosures is defined by the MEMS substrate, the second substrate, and a seal-ring between the MEMS substrate and the second substrate, wherein a first enclosure type has a first seal-ring type, wherein a second enclosure type has a second seal-ring type, wherein the second enclosure type comprises a gap of the seal ring of the second seal-ring type configured to allow a pressure differential between first enclosure type and the second enclosure type upon sealing the second enclosure type; and bonding the MEMS substrate with the second substrate. 11. The method of claim 10 , wherein the forming the MEMS substrate comprises forming the MEMS substrate such that the gap is defined by a predetermined separation of the second seal-ring type in a plane substantially parallel to the MEMS substrate. 12. The method of claim 10 , wherein the forming the MEMS substrate comprises forming the MEMS substrate such that the gap is defined by a difference in thickness of the first seal-ring type relative to the second seal-ring type and the second substrate, wherein the gap lies in a plane substantially orthogonal to the MEMS substrate. 13. The method of claim 10 , wherein the forming the MEMS substrate comprises forming the MEMS substrate such that the gap is defined by a dielectric layer between a MEMS device wafer and a MEMS handle wafer of the MEMS substrate. 14. The method of claim 13 , further comprising: forming a port through the MEMS handle wafer and dielectric layer proximate to the second enclosure type to establish gas flow resistance from the port to the second enclosure type via the gap; establishing a gas pressure and a gas composition at a predetermined value and a predetermined time to obtain, via controlled gas leak through the gap, a predetermined pressure and predetermined gas composition in the second enclosure type; sealing off the port by depositing a sealing material. 15. The method of claim 10 , wherein the boding comprises sealing the first enclosure type with the first seal-ring at a first pressure, at a first temperature, and at a first force applied to the MEMS substrate and the second substrate. 16. The method of claim 10 , wherein the boding comprises sealing the second enclosure type with the second seal-ring type at a second pressure, at a second temperature, and at a second force applied to the MEMS substrate and the second substrate. 17. The method of claim 16 , wherein the sealing the second enclosure type with the second seal-ring type comprises applying at least one of the second temperature or the second force applied at a predetermined value to seal the gap in the second enclosure type. 18. The method of claim 17 , wherein the sealing the second enclosure type comprises reflowing solder associated with at least one of the first seal-ring type or the second seal-ring type to seal the gap in the second enclosure type. 19. The method of claim 10 , wherein the contacting the MEMS substrate with the second substrate and the bonding the MEMS substrate with the second substrate comprises contacting the MEMS substrate with a complementary metal-oxide semiconductor (CMOS) substrate and bonding the MEMS substrate with the CMOS substrate.

Assignees

Inventors

Classifications

  • maintaining a controlled atmosphere with processes not provided for in B81C1/00285 · CPC title

  • characterised by the material or arrangement of seals between parts · CPC title

  • Packaging together an electronic processing unit die and a micromechanical structure die (MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261) · CPC title

  • Hermetically sealing an opening in the lid · CPC title

  • B81B7/02Primary

    containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title

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What does patent US10532926B2 cover?
A Microelectromechanical systems (MEMS) structure comprises a MEMS wafer. A MEMS wafer includes a handle wafer with cavities bonded to a device wafer through a dielectric layer disposed between the handle and device wafers. The MEMS wafer also includes a moveable portion of the device wafer suspended over a cavity in the handle wafer. Four methods are described to create two or more enclosures …
Who is the assignee on this patent?
Invensense Inc
What technology area does this patent fall under?
Primary CPC classification B81B7/02. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jan 14 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).