Charge carrier transport facilitated by strain

Patent metadata

Field	Value
Publication number	US-10529855-B2
Application number	US-201815964765-A
Country	US
Kind code	B2
Filing date	Apr 27, 2018
Priority date	Dec 30, 2014
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a layer of a first semiconductor material on top of a layer of a second semiconductor material, wherein the first semiconductor material and the second semiconductor material are lattice-matched, and wherein the second semiconductor layer is epitaxial with the first semiconductor layer;
etching the layer of first semiconductor material to a depth that, at least, exposes the second semiconductor material and forms a semiconductor channel region, wherein the semiconductor channel region has a first end and a second end; and
forming a first source/drain region at the first end of the semiconductor channel region and a second source/drain region at the second end of the semiconductor channel region, wherein the first source/drain region and the second source/drain region are further comprised of a third semiconductor material that is a ternary semiconductor material, wherein the third semiconductor material is lattice-mismatched to the first semiconductor material and to the second semiconductor material.

2. The method of claim 1 , wherein the etching step provides an isotropic etch.

3. The method of claim 1 further comprising:
fabricating a gate structure on top of the layer of the first semiconductor material.

4. The method of claim 1 further comprising:
fabricating a gate structure on top of the semiconductor channel region such that the gate structure is between the first source/drain region and the second source/drain region.

5. The method of claim 1 , wherein one or both of the first semiconductor material and the third semiconductor material are further comprised of compound semiconductors.

6. The method of claim 1 , wherein one or both of the first semiconductor material and the third semiconductor material are further comprised of III-V semiconductors.

7. The method of claim 1 , wherein one or both of the first semiconductor material and the third semiconductor material include indium.

8. The method of claim 1 , wherein one or both of the first semiconductor material and the third semiconductor material are further comprised of alloys of indium arsenide and gallium arsenide.

9. The method of claim 1 , wherein (i) at least a portion of the first semiconductor material is between the first source/drain region and the second source/drain region, and (ii) the at least portion has a degree of uniaxial strain that is based, at least in part, on a difference between a lattice structure of the first semiconductor material and a lattice structure of the third semiconductor material.

10. The method of claim 1 , wherein the first semiconductor material is comprised of In 0.53 Ga 0.47 As.

11. The method of claim 1 , wherein the third semiconductor material is comprised of In y Ga (1-y) As.

12. The method of claim 11 , wherein y has a range between 0 and approximately 0.53.

13. The method of claim 11 , wherein y has a range between approximately 0.53 and 1.

Assignees

• IBM

Inventors

• Basu Anirban
• Cohen Guy M

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/2909

  Phosphides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P50/646

  of Group III-V materials · CPC title