Image processing device

Patent metadata

Field	Value
Publication number	US-10529062-B2
Application number	US-201715623747-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Jun 29, 2016
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An image processing device includes a parameter processing circuit and an image correction circuit. The image processing device rearrange a plurality of parameters in order of a plurality of reference image data items written to an image memory. The image correction circuit includes a parameter memory, a pixel calculation circuit, an acquisition circuit, a comparison circuit, and a logic circuit. The image correction circuit reads one of one of the plurality of reference image data items from the image memory storing input image data and perform image correction on the one of the plurality of reference image data items to generate an output image corresponding to one of a plurality of output image areas.

First claim

What is claimed is:

1. An image processing device, comprising:
an image memory configured to store a plurality of parameters in a first order corresponding to a plurality of reference image data items, each of the plurality of parameters having a corresponding one of the plurality of reference image data items and the plurality of reference image data items corresponding to input image data which is to be reference data;
a parameter processing circuit configured to rearrange the plurality of parameters into a second order different from the first order; and
an image correction circuit configured to read one of the plurality of reference image data items from the image memory and perform image correction on the one of the plurality of reference image data items to generate an output image corresponding to one of a plurality of output image areas, wherein
the image correction circuit comprises:
a pixel calculation circuit configured to calculate a required number of pixels in a sub-scanning direction required to perform the image correction on the one of the plurality of reference image data items to generate the output image corresponding to the one of the plurality of output image areas based on the corresponding one of the plurality parameters from the second order;
an acquisition circuit configured to acquire a number of written pixels in the sub-scanning direction already written to the image memory in a middle of writing the input image data;
a first comparison circuit configured to compare the required number of pixels in the sub-scanning direction and the number of written pixels in the sub-scanning direction; and
a logic circuit configured to determine whether the one of the plurality reference image data items corresponding to the one of the plurality of parameters is to be acquired from the image memory based on a result of the comparison performed by the first comparison circuit.

2. The image processing device of claim 1 , wherein
the logic circuit activates a pending signal when the result of the comparison indicates that the number of written pixels in the sub-scanning direction already written to the image memory is smaller than the required number of pixels in the sub-scanning direction required to perform the image correction, and
the pending signal disables a read request signal to the image memory to read the reference image data items.

3. The image processing device of claim 2 , wherein the logic circuit deactivates the pending signal when the result of the comparison indicates that the number of written pixels in the sub-scanning direction already written to the image memory is equal to or larger than the required number of pixels in the sub-scanning direction required to perform the image correction.

4. The image processing device of claim 1 , further comprising a second comparison circuit configured to compare a first number of written pixels in the sub-scanning direction in association with a first camera and a second number of written pixels in the sub-scanning direction in association with a second camera and provide a smaller of the first number of written pixels and the second number of written pixels to the first comparison circuit,
wherein the first comparison circuit compares the smaller of the first number of written pixels in the sub-scanning direction and the second number of written pixels in the sub-scanning direction that is provided from the second comparison circuit and the required number of pixels in the sub-scanning direction.

5. The image processing device of claim 1 , wherein the pixel calculation circuit calculates the required number of pixels in the sub-scanning direction required to perform the image correction based on:
a head address of the one of the plurality of reference image data items corresponding to the one of the plurality of output image areas;
a number of pixels in a main scanning direction of the input image data; and
a number of pixels in the sub-scanning direction of the one of the reference image data items corresponding to the one of the plurality of output image areas.

6. The image processing device of claim 1 , wherein the parameter processing circuit rearranges the plurality of parameters into the second order by at least assigning priority to the one of the plurality of parameters corresponding to one of the plurality of output image areas having a minimum required number of pixels in the sub-scanning direction for the image correction in an area line.

7. The image processing device of claim 1 , wherein the parameter processing circuit rearranges the plurality of parameters into the second order by at least assigning priority to one of the plurality of parameters having a start position corresponding to an arbitrary one of the plurality of output image areas.

8. The image processing device of claim 1 , wherein the parameter processing circuit stores the plurality of parameters in the image memory in the second order.

9. The image processing device of claim 1 , wherein the parameter processing circuit rearranges the plurality of parameters into the second order which is an order in which the plurality of output image areas are generated.

10. The image processing device of claim 7 , wherein
output image data is divided into N of the plurality of output image areas in a main scanning direction and divided into M of the plurality of output image areas in the sub-scanning direction, resulting in MN of the plurality of output image areas as a total in the output image data,
the plurality of output image areas from 1 to N are defined as a first area line, and
the start position is one other than a position of the output image areas at 1 .

11. The image processing device of claim 1 , wherein the image correction circuit comprises a parameter memory configured to store each of the plurality of parameters used to read the corresponding one of the plurality of reference image data items from the image memory.

Assignees

• Okada Yasuhiro
• Ricoh Co Ltd

Inventors

• Okada Yasuhiro

Classifications

• G06T1/60

  Memory management · CPC title

• H04N23/81

  for suppressing or minimising disturbance in the image signal generation · CPC title

• H04N25/61

  the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4" · CPC title

• G06T5/50

  using two or more images, e.g. averaging or subtraction · CPC title

• G06T2200/28

  involving image processing hardware · CPC title