Apparatus and method for managing bounded pointers

Patent metadata

Field	Value
Publication number	US-10528490-B2
Application number	US-201615771107-A
Country	US
Kind code	B2
Filing date	Oct 19, 2016
Priority date	Dec 2, 2015
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An apparatus and method are provided for managing bounded pointers. The apparatus has processing circuitry to execute a sequence of instructions, and a plurality of storage elements accessible to the processing circuitry, for storage of bounded pointers and non-bounded pointers. Each bounded pointer has explicit range information associated therewith indicative of an allowable range of memory addresses when using the bounded pointer. A current range check storage element is then used to store a current range check state for the processing circuitry. When the current range check state indicates a default state, the processing circuitry is responsive to execution of a memory access instruction identifying a pointer to be used to identify a memory address, to perform a range check operation to determine whether access to that memory address is permitted. In particular, when the memory access instruction identifies as the pointer one of the bounded pointers, the range check operation is performed with reference to the explicit range information associated with that bounded pointer. If instead the memory access instruction identifies a non-bounded pointer, the range check operation is performed with reference to default range information defined for the processing circuitry. On detection of at least one event, the current range check state is set to an executive state. When in the executive state, the processing circuitry is responsive to execution of a memory access instruction to disable the range check operation when the identified pointer is a non-bounded pointer. This provides an efficient, but controlled, mechanism for enabling the set of bounded pointers available to the processing circuitry to be altered.

First claim

The invention claimed is:

1. An apparatus, comprising:
processing circuitry to execute a sequence of instructions;
a plurality of storage elements accessible to the processing circuitry, for storage of bounded pointers and non-bounded pointers, each bounded pointer having explicit range information associated therewith indicative of an allowable range of memory addresses when using said bounded pointer; and
a current range check storage element to store a current range check state for the processing circuitry;
when the current range check state indicates a default state, the processing circuitry being responsive to execution of a memory access instruction in the instruction sequence identifying a pointer to be used to identify a memory address, to perform a range check operation to determine whether access to that memory address is permitted, when the memory access instruction identifies as the pointer one of said bounded pointers the range check operation being performed with reference to the explicit range information associated with that bounded pointer, and when the memory access instruction identifies as the pointer one of said non-bounded pointers the range check operation being performed with reference to default range information defined for the processing circuitry;
on detection of at least one event, the current range check state being set to an executive state, and when in the executive state the processing circuitry being responsive to execution of said memory access instruction to disable the range check operation when the identified pointer is a non-bounded pointer.

2. An apparatus as claimed in claim 1 , wherein said at least one event comprises taking of an exception by the processing circuitry.

3. An apparatus as claimed in claim 2 , further comprising:
a saved range check storage element to store a saved range check state;
on taking of the exception the saved range check storage element being updated to store as the saved range check state the current range check state used by the processing circuitry prior to the current range check state being set to the executive state in response to the exception being taken.

4. An apparatus as claimed in claim 3 , wherein on return from the exception the current range check storage element is updated to identify as the current range check state the saved range check state.

5. An apparatus as claimed in claim 2 , wherein on taking the exception the processing circuitry is arranged to perform an exception handling operation during which one or more memory accesses are performed whilst in the executive state to alter a set of bounded pointers that will be available to the processing circuitry on return from the exception.

6. An apparatus as claimed in claim 1 , wherein when in the executive state the processing circuitry is responsive to execution of said memory access instruction to further disable the range check operation when the identified pointer is a bounded pointer.

7. An apparatus as claimed in claim 1 , further comprising a default range storage element to store the default range information.

8. An apparatus as claimed in claim 1 , wherein:
the processing circuitry is arranged to issue a fetch memory address to identify an instruction to be fetched for subsequent execution by the processing circuitry, when in the default state the processing circuitry being arranged to perform a fetch range check operation prior to issuing the fetch memory address in order to determine, with reference to default fetch range information defined for the processing circuitry, whether access to the fetch memory address is permitted; and
when in the executive state the processing circuitry being arranged to disable the fetch range check operation.

9. An apparatus as claimed in claim 8 , wherein the fetch memory address is determined by a program counter value and the default fetch range information is program counter range information.

10. An apparatus as claimed in claim 1 , wherein the processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege, and the processing circuitry being arranged, in response to at least a subset of exceptions taken by the processing circuitry, to change the exception level that it is operating at.

11. An apparatus as claimed in claim 10 , wherein, when the processing circuitry is operating at at least one of the exception levels, the current range check state is changeable between the executive state and the default state whilst remaining at the same exception level.

12. An apparatus as claims in claim 3 , wherein:
the processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege, and the processing circuitry being arranged, in response to at least a subset of exceptions taken by the processing circuitry, to change the exception level that it is operating at; and
taking the exception causes the processing circuitry to transition from a first exception level to a second exception level, the saved range state storage element is updated to identify the range check state being used by the processing circuitry at the first exception level prior to the exception being taken, and the current range check state is set to the executive state on transitioning the processing circuitry to the second exception level.

13. An apparatus as claimed in claim 12 , wherein during operation at the second exception level the processing circuitry is arranged to change the current range check state from the executive state to the default state.

14. An apparatus as claimed in claim 13 , wherein on return from the exception the processing circuitry is arranged to transition back to the first exception level, and the current range check storage element is updated to identify as the current range check state the saved range check state unless this would cause the current range check state to change from the default state to the executive state on return from the exception.

15. An apparatus as claimed in claim 1 , further comprising:
an access control storage element having one or more fields, each field being associated with a corresponding set of functionality and having a value indicating accessibility of that corresponding set of functionality to the processing circuitry when the processing circuitry is in said default state;
when in the executive state, the processing circuitry's access to each corresponding set of functionality being independent of the associated value in the access control storage.

16. An apparatus as claimed in claim 15 , wherein in the default state the processing circuitry is prevented from updating the access control storage element.

17. A method of operating an apparatus having processing circuitry to execute a sequence of instructions, and a plurality of storage elements for storage of bounded pointers and non-bounded pointers for access by the processing circuitry, each bounded pointer having explicit range information associated therewith indicative of an allowable range of memory addresses when using said bounded pointer, the method comprising:
storing a current range check state for the processing circuitry;
when the current range check state indicates a default state, then responsive to execution of a memory access instruction in the instruction sequence identifying a pointer to be used to identify a memory address, performing a range check operation to determine whether access to that memory address is permitted, when the memory access instruction id

Assignees

• Advanced Risc Mach Ltd

Inventors

• Barnes Graeme Peter

Classifications

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F12/1441 Primary

  for a range · CPC title