Pseudo-invalidating dynamic address translation (DAT) tables of a DAT structure associated with a workload

Patent metadata

Field	Value
Publication number	US-10528477-B2
Application number	US-201715494618-A
Country	US
Kind code	B2
Filing date	Apr 24, 2017
Priority date	Apr 24, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A computer-implemented method includes pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload. A page fault occurring during translation of a virtual memory address of data required by the workload is detected. Responsive to the page fault, the DAT structure is traversed. The DAT structure includes one or more DAT tables, and each DAT entry in each of the one or more DAT tables is associated with an in-use bit indicating whether the DAT entry is in use. Traversing the DAT structure includes pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred; and identifying a first page frame referenced by the virtual memory address for which the page fault occurred. The data in the first page frame is processed responsive to the page fault.

First claim

What is claimed is:

1. A computer-implemented method comprising:
pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload, wherein the pseudo-invalidating the first DAT table comprises marking each DAT entry in the first DAT table as invalid;
detecting a page fault occurring during translation of a virtual memory address of data required by the workload;
traversing the DAT structure, responsive to the page fault, wherein the DAT structure is configured to translate virtual memory addresses to physical memory addresses, wherein the DAT structure comprises one or more DAT tables, and wherein each DAT entry in each of the one or more DAT tables is associated with an in-use bit indicating whether the DAT entry is in use;
wherein the traversing comprises:
pseudo-invalidating, by a computer processor, each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred; and
identifying a first page frame referenced by the virtual memory address for which the page fault occurred; and

processing the data in the first page frame responsive to the page fault occurring during translation of the virtual memory address of the data required by the workload, wherein the pseudo-invalidating the first DAT table of the DAT structure is responsive to detecting that the workload has been moved from a first cluster of processor cores to a second cluster of processor cores and the processing the data in the first page frame responsive to the page fault occurring during translation of the virtual memory address of the data required by the workload comprises:
identifying a second page frame located closer than the first page frame to the workload that has been moved; and
copying data from the first page frame to the second page frame, responsive to the workload having been moved and responsive to the page fault.

2. The computer-implemented method of claim 1 , wherein a first DAT entry of the first DAT table is associated with a valid in-use bit when pseudo-invalidated.

3. The computer-implemented method of claim 1 , wherein the pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred further comprises iteratively pseudo-invalidating each DAT entry referenced by a higher-level DAT entry involved in translating the virtual memory address for which the page fault occurred.

4. The computer-implemented method of claim 3 , wherein the iteratively pseudo-invalidating each DAT entry referenced by a higher-level DAT entry involved in translating the virtual memory address for which the page fault occurred comprises, for a first DAT entry of the one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred:
identifying a lower-level DAT entry involved in translating the virtual memory address for which the page fault occurred;
pseudo-invalidating the lower-level DAT entry; and
validating the first DAT entry.

5. The computer-implemented method of claim 1 , wherein the pseudo-invalidating each of the one or more DAT entries that are involved in translating the virtual memory address for which the page fault occurred comprises marking each of the one or more DAT entries as invalid.

6. A system comprising:
a memory having computer-readable instructions; and
one or more processors for executing the computer-readable instructions, the computer-readable instructions comprising:
pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload, wherein the pseudo-invalidating the first DAT table comprises marking each DAT entry in the first DAT table as invalid;
detecting a page fault occurring during translation of a virtual memory address of data required by the workload;
traversing the DAT structure, responsive to the page fault, wherein the DAT structure is configured to translate virtual memory addresses to physical memory addresses, wherein the DAT structure comprises one or more DAT tables, and wherein each DAT entry in each of the one or more DAT tables is associated with an in-use bit indicating whether the DAT entry is in use;
wherein the traversing comprises:
pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred; and
identifying a first page frame referenced by the virtual memory address for which the page fault occurred; and

processing the data in the first page frame responsive to the page fault occurring during translation of the virtual memory address of the data required by the workload, wherein the pseudo-invalidating the first DAT table of the DAT structure is responsive to detecting that the workload has been moved from a first cluster of processor cores to a second cluster of processor cores and the processing the data in the first page frame responsive to the page fault occurring during translation of the virtual memory address of the data required by the workload comprises:
identifying a second page frame located closer than the first page frame to the workload that has been moved; and
copying data from the first page frame to the second page frame, responsive to the workload having been moved and responsive to the page fault.

7. The system of claim 6 , wherein a first DAT entry of the first DAT table is associated with a valid in-use bit when pseudo-invalidated.

8. The system of claim 6 , wherein the pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred further comprises iteratively pseudo-invalidating each DAT entry referenced by a higher-level DAT entry involved in translating the virtual memory address for which the page fault occurred.

9. The system of claim 8 , wherein the iteratively pseudo-invalidating each DAT entry referenced by a higher-level DAT entry involved in translating the virtual memory address for which the page fault occurred comprises, for a first DAT entry of the one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred:
identifying a lower-level DAT entry involved in translating the virtual memory address for which the page fault occurred;
pseudo-invalidating the lower-level DAT entry; and
validating the first DAT entry.

10. The system of claim 6 , wherein the pseudo-invalidating each of the one or more DAT entries that are involved in translating the virtual memory address for which the page fault occurred comprises marking each of the one or more DAT entries as invalid.

11. A computer-program product for selectively processing data associated with a workload, the computer-program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload, wherein the pseudo-invalidating the first DAT table comprises marking each DAT entry in the first DAT table as invalid;
detecting a page fault occurring during translation of a virtual memory address of data required by the workload;
traversing the DAT structure, responsive to the page fault, wherein the DAT structure is configured to translate virtual memory addresses to physical memory addresses, wherein

Assignees

• IBM

Inventors

• Mari Charles E
• Partlow Steven M
• Tzortzatos Elpida

Classifications

• G06F2212/683

  Invalidation · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F2212/1024

  Latency reduction · CPC title