Validation of multiprocessor hardware component

Patent metadata

Field	Value
Publication number	US-10528443-B2
Application number	US-201514610167-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

First claim

What is claimed is:

1. A method performed by a heterogeneous system architecture hardware component to be validated, wherein the heterogeneous system architecture hardware component having a plurality of hardware processing units each belonging to one of at least two types, such that one of the at least two types of hardware processing units is less error-prone than a remainder of the at least two types, the method comprising:
designating as a manager processing unit one of the hardware processing units of the heterogeneous system architecture hardware component under validation that belongs to the less error-prone type, wherein the less error-prone type is of a more mature design and is more reliable than the remainder of the at least two types; and
performing initialization and run-time monitoring of the hardware component in a reliable manner, comprising:
initiating, by the manager processing unit, execution of a tester program code for testing hardware processing units by hardware processing units of the heterogeneous system architecture hardware component other than the manager processing unit;
monitoring by the manager processing unit the status of the hardware processing units during execution of the tester program code;
creating a data record by the manager processing unit, wherein the data record comprises data related to a test failure detected during execution of the tester program code; and,
halting, by the manager processing unit, execution of the tester program code by hardware processing units of the heterogeneous system architecture hardware component other than the manager processing unit upon detection of a test failure and prior to the data record creation.

2. The method of claim 1 , further comprising performing, by the manager processing unit, an initialization procedure prior to execution of the tester program code.

3. The method of claim 2 , wherein the initialization procedure by the manager processing unit comprises initializing other system components required by the heterogeneous system architecture hardware component undergoing validation during execution of the tester program code.

4. The method of claim 1 , wherein said designation of manager processing unit is determined after the tester program code has been loaded onto the heterogeneous system architecture hardware component under validation.

5. The method of claim 1 , wherein said designation of manager processing unit is predetermined prior to the loading of the tester program code onto the heterogeneous system architecture hardware component under validation.

6. The method of claim 1 , wherein the at least two types of hardware processing units of the heterogeneous system architecture hardware component under validation are functionally identical.

7. The method of claim 6 , wherein the at least two types of hardware processing units of the heterogeneous system architecture hardware component under validation differ in hardware complexity.

8. The method of claim 6 , wherein the at least two types of hardware processing units of the heterogeneous system architecture hardware component under validation differ in physical design.

9. The method of claim 6 , wherein the heterogeneous system architecture hardware component under validation employs a “big\LITTLE” system architecture.

10. The method of claim 6 , wherein the manager processing unit and other processing units of the heterogeneous system architecture hardware component under validation employ Shared Memory Architecture (SMA) and are cache coherent.

11. An apparatus incorporated within a heterogeneous system architecture hardware component to be validated, wherein the heterogeneous system architecture hardware component having a plurality of hardware processing units each belonging to one of at least two types, such that one of the at least two types of hardware processing units is less error-prone than a remainder of the at least two types, the apparatus comprising:
a designation component for designating as a manager processing unit one of the hardware processing units of the heterogeneous system architecture hardware component under validation that belongs to the less error-prone type, wherein the less error-prone type is of a more mature design and is more reliable than the remainder of the at least two types;
a monitoring component for monitoring by the manager processing unit in a reliable manner the status of the hardware processing units during execution of a tester program code, the monitoring component comprising a test starter component for initiating execution of the tester program code for testing processing units by hardware processing units of the heterogeneous system architecture hardware component other than the manager processing unit;
a data dumping component for creating a data record by the manager processing unit, wherein the data record comprises data related to a test failure detected during execution of the tester program code; and
a halting component for halting, by the manager processing unit, execution of the tester program code by hardware processing units of the heterogeneous system architecture hardware component other than the manager processing unit upon detection of a test failure and prior to the data record creation.

12. The apparatus of claim 11 , further comprising an initialization component for performing, by the manager processing unit, an initialization procedure prior to execution of the tester program code.

13. The apparatus of claim 11 , wherein said designation component further comprises a determination component for determining the manager processing unit designation.

14. A computer program product comprising a non-transitory computer readable storage medium retaining program instructions for execution by a heterogeneous system architecture hardware component to be validated, wherein the heterogeneous system architecture hardware component having a plurality of hardware processing units each belonging to one of at least two types, such that one of the at least two types of hardware processing units is less error-prone than a remainder of the at least two types, the product comprising:
a first section of program instructions for designating as a manager processing unit one of the hardware processing units of the heterogeneous system architecture hardware component under validation that belongs to the less error-prone type, wherein the less error-prone type is of a more mature design and is more reliable than the remainder of the at least two types;
a second section of program instructions for initiating execution, by the manager processing unit, of a tester program code for testing processing units by hardware processing units of the heterogeneous system architecture hardware component other than the manager processing unit;
a third section of program instructions for monitoring by the manager processing unit in a reliable manner the status of the hardware processing units during execution of the tester program code;
a fourth section of program instructions for creating a data record by the manager processing unit, wherein the data record comprises data related to a test failure detected during execution of the tester program code; and,
a fifth section of program instructions for halting, by the manager processing unit, execution of the tester program code by hardware processing units of the heterogeneous system architecture hardware component other than the manager processing unit upon detection of a test failure and prior to the data record creation.

15. The computer program product of claim 14 , further comprising an additional

Assignees

• Samsung Ltd
• IBM
• Samsung Electronics Co Ltd

Inventors

• Park Sung-Boem
• Nahir Amir
• Sokhin Vitali
• Kadry Wisam
• Park Jin Sung
• Cho Ara

Classifications

• G06F11/3055

  Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16) · CPC title

• G06F11/2242 Primary

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title