Mapping around defective flash memory of a storage array

Patent metadata

Field	Value
Publication number	US-10528419-B2
Application number	US-201715705691-A
Country	US
Kind code	B2
Filing date	Sep 15, 2017
Priority date	Aug 7, 2014
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A method of failure mapping is provided. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

First claim

What is claimed is:

1. A method of failure mapping in a storage system, performed by the storage system, comprising:
determining a failed flash memory die in storage memory of the storage system;
generating a defect map comprising a physical memory address associated with the failed flash memory die, wherein the defect map comprises one of a plurality of masks in a hierarchical mask set used for generating page masks;
mapping around the physical memory address associated with the failed flash memory die based on the defect map; and
writing to or reading from the storage memory, in accordance with the mapping.

2. The method of claim 1 , further comprising:
recording an indication of the failed flash memory die in a defects map.

3. The method of claim 1 , further comprising:
generating an address translation table that maps around the failed flash memory die.

4. The method of claim 1 , further comprising:
obtaining information about the failed flash memory die from a source external to the storage system, wherein the determining is based on the information from the source external to the storage system.

5. The method of claim 1 , further comprising:
performing yield recovery of a flash package with one or more known defective flash dies.

6. The method of claim 1 , further comprising:
determining diagnostic information of the storage memory, on a per flash die basis.

7. The method of claim 1 , further comprising:
performing graceful degradation of storage capacity of the storage system, based on the mapping around the failed flash memory die and mapping around further failed flash memory dies.

8. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:
determining one or more flash memory dies are defective in storage memory of a storage system;
generating a defect map comprising physical memory addresses associated with the one or more flash memory dies that are defective, wherein the defect map comprises one of a plurality of masks in a hierarchical mask set used for generating page masks;
mapping around the physical memory addresses associated with the one or more flash memory dies that are defective based on the defect map; and
writing to or reading from the storage memory, through the mapping.

9. The computer-readable media of claim 8 , wherein the method further comprises:
writing information regarding the one or more flash memory dies that are defective to a defects map.

10. The computer-readable media of claim 8 , wherein the method further comprises:
generating an address translation table in accordance with the mapping, wherein the writing to or reading from the storage memory is through the address translation table.

11. The computer-readable media of claim 8 , wherein the method further comprises:
writing into the storage system, information that the one or more flash memory dies are defective from a manufacturer of the one or more flash memory dies, wherein the determining is based on the information from the manufacturer.

12. The computer-readable media of claim 8 , wherein the mapping and the writing or reading supports yield recovery of a flash package with one or more known defective flash dies.

13. The computer-readable media of claim 8 , wherein the method further comprises:
performing diagnostics on the storage memory, on a per flash die basis, wherein the determining is based on the diagnostics.

14. A storage system, comprising:
flash memory-based storage memory; and
one or more processors, configurable to:
determine one or more failed flash memory dies in the storage memory;
generate a defect map comprising physical memory addresses associated with the one or more failed flash memory dies, wherein the defect map comprises one of a plurality of masks in a hierarchical mask set used for generating page masks;
develop mapping around the physical memory addresses associated with the one or more failed flash memory dies based on the defect map; and
write to or read from the storage memory, using the mapping.

15. The storage system of claim 14 , wherein the one or more processors are further configurable to:
generate or update a defects map to indicate the one or more failed flash memory dies.

16. The storage system of claim 14 , wherein the one or more processors are further configurable to:
generate or update an address translation table to map around the one or more failed flash memory dies.

17. The storage system of claim 14 , wherein the one or more processors are further configurable to:
incorporate information about the one or more failed flash memory dies from a source external to the storage system.

18. The storage system of claim 14 , wherein the one or more processors are further configurable to:
recover usage of a flash package with one or more defective flash dies.

19. The storage system of claim 14 , wherein the one or more processors are further configurable to:
diagnose the storage memory, on a per flash die basis.

20. The storage system of claim 14 , wherein the one or more processors are further configurable to:
perform graceful degradation of storage capacity of the storage system, based on the mapping around the one or more failed flash memory dies.

Assignees

• Pure Storage Inc

Inventors

• Davis John D
• Hayes John
• Kannan Hari
• Miladinovic Nenad
• Tan Zhangxi

Classifications

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F11/1008

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G11C29/883

  using a single defective memory device with reduced capacity, e.g. half capacity · CPC title

• G11C29/76

  using address translation or modifications · CPC title