Watchdog monitoring system that utilizes a disable application to monitor operation of an enable application

US10528409B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10528409-B2
Application numberUS-201815974010-A
CountryUS
Kind codeB2
Filing dateMay 8, 2018
Priority dateJul 31, 2017
Publication dateJan 7, 2020
Grant dateJan 7, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A watchdog monitoring system having a watchdog integrated circuit and a microcontroller is provided. The microcontroller has a microprocessor, and a digital input/output device with an enable pin and a disable pin. A disable application in the microcontroller monitors the enable pin of the digital input-output device, and if the enable pin does not have a high logic state within a predetermined amount of time after a first time indicating that the microcontroller is malfunctioning, then the disable application generates a control message.

First claim

Opening claim text (preview).

What is claimed is: 1. A watchdog monitoring system, comprising: a watchdog integrated circuit having an enable pin and a disable pin; a microcontroller having a microprocessor, and a digital input/output device with an enable pin and a disable pin, the enable pin of the digital input-output device being electrically coupled to the enable pin of the watchdog integrated circuit, the disable pin of the digital input-output device being electrically coupled to the disable pin of the watchdog integrated circuit; the microprocessor having an enable application and a disable application; the enable application commanding the enable pin of the digital input-output device to transition from a high logic state to a low logic state at a first time that indicates an enable state has been initiated, and in response the watchdog integrated circuit starts an internal timer; the disable application commanding the disable pin of the digital input-output device to transition from the high logic state to the low logic state at a second time that indicates a disable state has been initiated, and in response the watchdog integrated circuit stops the internal timer; and the disable application monitoring the enable pin of the digital input-output device, and if the enable pin of the digital input-output device does not have the high logic state within a predetermined amount of time after the second time indicating that the microcontroller is malfunctioning, then the disable application generates a control message. 2. The watchdog monitoring system of claim 1 , wherein the control message induces the microcontroller to transition at least one of a high voltage switch and a low voltage switch in a DC-DC voltage converter to an open operational state. 3. The watchdog monitoring system of claim 1 , wherein the control message induces the microcontroller to transition a contactor to the open operational state. 4. A watchdog monitoring system, comprising: a watchdog integrated circuit having an enable pin and a disable pin; a microcontroller having a microprocessor, and a digital input/output device with an enable pin and a disable pin; the enable pin of the digital input-output device being electrically coupled to the enable pin of the watchdog integrated circuit, the disable pin of the digital input-output device being electrically coupled to the disable pin of the watchdog integrated circuit; the microprocessor having an enable application and a disable application; the enable application commanding the enable pin of the digital input-output device to transition from a high logic state to a low logic state at a first time that indicates an enable state has been initiated, and in response the watchdog integrated circuit starts an internal timer; the disable application commanding the disable pin of the digital input-output device to transition from the high logic state to the low logic state at a second time that indicates a disable state has been initiated, and in response the watchdog integrated circuit stops the internal timer within the watchdog integrated circuit; the enable application commanding the enable pin of the digital input-output device to transition from the low logic state to the high logic state at a third time; and the disable application monitoring the enable pin of the digital input-output device, and if the enable pin of the digital input-output device has the high logic state at a fourth time which corresponds to a predetermined amount of time after the third time indicating that the microcontroller is malfunctioning, then the disable application generates a control message. 5. The watchdog monitoring system of claim 4 , wherein the control message induces the microcontroller to transition at least one of a high voltage switch and a low voltage switch in a DC-DC voltage converter to an open operational state. 6. The watchdog monitoring system of claim 4 , wherein the control message induces the microcontroller to transition a contactor to the open operational state.

Assignees

Inventors

Classifications

  • within a central processing unit [CPU] · CPC title

  • with digital control · CPC title

  • The other DC source being a battery actively interacting with the first one, i.e. battery to battery charging (with circuits for polarity protection H02J7/68) · CPC title

  • Two-wire DC power distribution systems · CPC title

  • by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

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What does patent US10528409B2 cover?
A watchdog monitoring system having a watchdog integrated circuit and a microcontroller is provided. The microcontroller has a microprocessor, and a digital input/output device with an enable pin and a disable pin. A disable application in the microcontroller monitors the enable pin of the digital input-output device, and if the enable pin does not have a high logic state within a predetermined…
Who is the assignee on this patent?
Lg Chemical Ltd
What technology area does this patent fall under?
Primary CPC classification G06F11/0757. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).