Information processing apparatus, multithread matrix operation method, and multithread matrix operation program

Patent metadata

Field	Value
Publication number	US-10528384-B2
Application number	US-201815978761-A
Country	US
Kind code	B2
Filing date	May 14, 2018
Priority date	May 23, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An information processing apparatus includes a memory; and a processor. The processor is configured to execute partitioning a predetermined matrix whose values of elements are to be generated by a matrix operation, into a predetermined number of first submatrices whose dimension in at least one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers used for the matrix operation, and into the predetermined number of second submatrices that are different from the predetermined number of the first submatrices; and assigning a matrix operation to generate values of elements of each of the predetermined number of the first submatrices, and a matrix operation to generate values of elements of each of the predetermined number of the second submatrices, to each of the predetermined number of threads.

First claim

What is claimed is:

1. An information processing apparatus comprising:
a memory; and
a processor configured to execute partitioning a primary submatrix of a predetermined matrix whose values of elements are to be generated by a matrix operation, into a number of first submatrices whose dimension in one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers of the processor used to perform the matrix operation, and partitioning a secondary submatrix of the predetermined matrix from which the primary submatrix is removed into a same number of second submatrices that are different from the first submatrices;
assigning first matrix operations, each provided to generate values of elements of a corresponding one of the first submatrices, to a same number of threads, respectively, and assigning second matrix operations, each provided to generate values of elements of a corresponding one of the second submatrices, to the number of threads, respectively;
executing the first matrix operations to generate the values of the elements of each of the first submatrices in the case where the first matrix operations are assigned to the threads, and executing the second matrix operations to generate the values of the elements of each of the second submatrices in the case where the second matrix operations are assigned to the threads;
obtaining from the threads the values of the elements of each of the first submatrices in a case where the first matrix operations are assigned to the threads, and obtaining from the threads the values of the elements of each of the second submatrices in a case where the second matrix operations are assigned to the threads;
combining the obtained values of the elements of each of the first submatrices and the obtained values of the elements of each of the second submatrices to generate the values of the elements of the predetermined matrix; and
outputting the generated values of the elements of the predetermined matrix to an external device.

2. The information processing apparatus as claimed in claim 1 , wherein the partitioning partitions the predetermined matrix into the number of the first submatrices whose dimension in the row direction is a multiple of the block size, and into the same number of the second submatrices.

3. The information processing apparatus as claimed in claim 1 , wherein the partitioning partitions the predetermined matrix into the number of the first submatrices whose dimension in the column direction is a multiple of the block size, and into the same number of the second submatrices.

4. The information processing apparatus as claimed in claim 1 , wherein the partitioning compares a first remainder obtained by dividing the dimension in the row direction of the predetermined matrix by the block size, with a second remainder obtained by dividing the dimension in the column direction of the predetermined matrix by the block size,
as a result of the comparison, in a case where the first remainder is smaller than the second remainder, partitions the predetermined matrix into the number of the first submatrices whose dimension in the row direction is a multiple of the block size, and into the same number of the second submatrices, and
as a result of the comparison, in a case where the first remainder is greater than the second remainder, partitions the predetermined matrix into the number of the first submatrices whose dimension in the column direction is a multiple of the block size, and into the same number of the second submatrices.

5. The information processing apparatus as claimed in claim 1 , wherein the predetermined number of the threads are implemented by the predetermined number of arithmetic logic units, respectively.

6. A multithread matrix operation method executed by a computer, the method comprising:
partitioning a primary submatrix of a predetermined matrix whose values of elements are to be generated by a matrix operation, into a number of first submatrices whose dimension in one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers of a processor used to perform the matrix operation, and partitioning a secondary submatrix of the predetermined matrix from which the primary submatrix is removed into a same number of second submatrices that are different from the first submatrices;
assigning first matrix operations, each provided to generate values of elements of a corresponding one of the first submatrices, to a same number of threads, respectively, and assigning second matrix operations, each provided to generate values of elements of a corresponding one of the second submatrices, to the number of threads, respectively;
executing the first matrix operations to generate the values of the elements of each of the first submatrices in the case where the first matrix operations are assigned to the threads, and executing the second matrix operations to generate the values of the elements of each of the second submatrices in the case where the second matrix operations are assigned to the threads;
obtaining from the threads the values of the elements of each of the first submatrices in a case where the first matrix operations are assigned to the threads, and obtaining from the threads the values of the elements of each of the second submatrices in a case where the second matrix operations are assigned to the threads;
combining the obtained values of the elements of each of the first submatrices and the obtained values of the elements of each of the second submatrices to generate the values of the elements of the predetermined matrix; and
outputting the generated values of the elements of the predetermined matrix to an external device.

7. A non-transitory computer-readable recording medium having a program stored therein for causing a computer to execute a process of multithread matrix operations executed by a computer, the process comprising:
partitioning a primary submatrix of a predetermined matrix whose values of elements are to be generated by a matrix operation, into a number of first submatrices whose dimension in one of a row direction and a column direction is a multiple of a block size corresponding to a number of registers of a processor used to perform the matrix operation, and partitioning a secondary submatrix of the predetermined matrix from which the primary submatrix is removed into a same number of second submatrices that are different from the first submatrices;
assigning first matrix operations, each provided to generate values of elements of a corresponding one of the first submatrices, to a same number of threads, respectively, and assigning second matrix operations, each provided to generate values of elements of a corresponding one of the second submatrices, to the number of threads, respectively;
executing the first matrix operations to generate the values of the elements of each of the first submatrices in the case where the first matrix operations are assigned to the threads, and executing the second matrix operations to generate the values of the elements of each of the second submatrices in the case where the second matrix operations are assigned to the threads;
obtaining from the threads the values of the elements of each of the first submatrices in a case where the first matrix operations are assigned to the threads, and obtaining from the threads the values of the elements of each of the second submatrices in a case where the second matrix operations are assigned to the threads;
combining the obtained values of the elements of each of the first submatrices and the obtained values of the elements of each of the second submatrices to generate the values of the elements of the predetermined matr

Assignees

• Fujitsu Ltd

Inventors

• Takeshige Kazuaki

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/48 Primary

  Program initiating; Program switching, e.g. by interrupt · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title