Circuit for addition of multiple binary numbers

Patent metadata

Field	Value
Publication number	US-10528323-B2
Application number	US-201816145311-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 26, 2016
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

First claim

What is claimed is:

1. A circuit for addition of multiple binary numbers, the circuit comprising a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor, wherein the 4-to-2-compressor comprises a first sub-circuit and a second sub-circuit, wherein each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation of a compressed representation from three binary numbers, and wherein the 4-to-2-compressor comprises at least one bit cell associated with the first sub-circuit and associated with the second sub-circuit.

2. The circuit of claim 1 , wherein:
the at least one bit cell comprises a first sub-cell belonging to the first sub-circuit and a second sub-cell belonging to the second sub-circuit.

3. The circuit of claim 2 , wherein:
at least one of the first sub-cell and the second sub-cell comprises three operand inputs, an inverted sum output and an inverted carry output.

4. The circuit of claim 3 , wherein the three operand inputs of the first sub-cell and one operand input of the second sub-cell correspond to four operand inputs of the bit cell of the 4-to-2 compressor.

5. The circuit of claim 3 , wherein one operand input of the second sub-cell corresponds to a carry input of the bit cell.

6. The circuit of claim 3 , wherein an inverted sum output of the second sub-cell corresponds to a sum output of the bit cell and an inverted carry output of the first sub-cell corresponds to an inverted carry output of the bit cell.

7. The circuit of claim 3 , wherein the inverted sum output of the first sub-cell is connected to an operand input of the second sub-cell.

8. The circuit of claim 3 , wherein:
at least one of the first sub-cell and the second sub-cell comprises a XNOR-circuit transmitting the result of a XNOR operation on the three operand inputs as the inverted carry output.

9. The circuit of claim 8 , wherein:
wherein the first sub-cell comprises a NOR-circuit transmitting the result of a NOR operation on the three operand inputs as the inverted sum output.

10. The circuit of claim 8 , wherein:
the at least one of the first sub-cell and the second sub-cell comprises an AND-circuit receiving from a NAND-circuit the result of a NAND operation on the three operand inputs and an inverted carry output and transmitting the result as the inverted sum output.

11. The circuit of claim 2 , wherein:
the second sub-cell comprises a first XOR-circuit.

12. The circuit of claim 2 , wherein:
the second sub-cell is identical to the first sub-cell.

13. The circuit of claim 2 , wherein:
the second sub-cell is different from the first sub-cell.

14. The circuit of claim 1 , wherein the compressed representation comprises a result word and an inverted carry word and wherein the circuit comprises a conversion circuit for converting the compressed representation into a binary representation of the sum of the multiple binary numbers.

Assignees

• IBM

Inventors

• Beck Manuel
• Haller Wilhelm
• Krauch Ulrich
• Lind Kurt
• Schroeder Friedrich

Classifications

• G06F7/509 Primary

  for multiple operands, e.g. digital integrators · CPC title

• G06F7/50 Primary

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title