System and method for channel time management in solid state memory drives

Patent metadata

Field	Value
Publication number	US-10528268-B2
Application number	US-201715701966-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Sep 12, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

In one embodiment, a solid state storage drive comprises a plurality of flash memory devices communicatively coupled to a bus and a channel controller communicatively coupled to the bus, the channel controller comprising an execution time calculator configured to determine an aggregate execution time duration for a sequence of commands in a command execution queue based on a data transfer rate presently assigned for communications over the bus, and a channel execution unit configured to determine when to place a second command in a command execution queue based at least in part on the aggregate execution time duration. In one embodiment, the execution time calculator is further configured to determine the aggregate execution time duration based on the data transfer rate and a data payload quantity associated with at least one command in the sequence of commands.

First claim

What is claimed is:

1. A solid state storage drive comprising:
a plurality of flash memory devices communicatively coupled to a bus; and
a channel controller communicatively coupled to the bus, the channel controller comprising
an execution time calculator configured to determine an aggregate execution time duration for a sequence of commands in a command execution queue based on a data transfer rate for communications over the bus, the data payload quantity associated with the at least one command, and a number representing a quantity of error correction coding bits, and
a channel execution unit configured to determine when to place a second command in the command execution queue based at least in part on the aggregate execution time duration.

2. The solid state storage drive of claim 1 , wherein the execution time calculator is further configured to determine the aggregate execution time duration based on the data transfer rate for communications over the bus and a data payload quantity associated with at least one command in the sequence of commands.

3. The solid state storage drive of claim 1 , wherein the execution time calculator is further configured to recalculate the aggregate execution time duration when one of the sequence of commands is removed from the command execution queue.

4. The solid state storage drive of claim 1 , execution time calculator is further configured to recalculate the aggregate execution time duration when the second command is added to the command execution queue.

5. The solid state storage drive of claim 1 , wherein the channel execution unit is configured to determine when to place the second command in the command execution queue so as to satisfy at least one timing requirement of at least one of the plurality of flash memory devices.

6. The solid state storage drive of claim 5 , wherein the at least one timing requirement is one of a maximum erase time, a maximum suspend erase time, a maximum write time, and a maximum read time.

7. The solid state storage drive of claim 1 , wherein the channel controller further comprises a register configured to receive the aggregate execution time duration from the execution time calculator, and wherein the channel execution unit is configured to read the aggregate execution time duration from the register.

8. The solid state storage drive of claim 1 , wherein the second command is a read command or a write command.

9. The solid state storage drive of claim 1 , wherein the data transfer rate for communications over the bus was assigned to the channel controller during initialization of the channel controller.

10. A method comprising:
receiving a data transfer rate for communications over a bus communicatively coupled to a plurality of flash memory devices;
receiving a first command for one of the plurality of flash memory devices in a command execution queue;
calculating an execution time duration for the first command based on the data transfer rate;
calculating an aggregate execution time duration for a sequence of commands in the command execution queue based on the data transfer rate, the sequence of commands including the first command; and
determining when to place a second command in a command execution queue for the plurality of flash memory devices based at least in part on the aggregate execution time duration.

11. The method of claim 10 , further comprising
receiving a data payload quantity associated with the first command, and
wherein calculating the execution time duration for the first command is based on the data transfer rate and the data payload quantity associated with the first command.

12. The method of claim 11 , wherein calculating the execution time duration for the first command is based on the data transfer rate, the data payload quantity associated with the first command, and a number representing a quantity of error correction coding bits.

13. The method of claim 10 , wherein calculating the aggregate execution time duration includes subtracting an execution time duration for a command removed from the command execution queue.

14. The method of claim 10 , further comprising
calculating an execution time duration for the second command based on the data transfer rate when the second command has been placed in the command execution queue; and
calculating the aggregated execution time duration for the sequence of commands in the command execution queue, the sequence of commands including the second command.

15. The method of claim 10 , wherein determining when to place the second command in the command execution queue is based at least in part on at least one timing requirement of at least one of the plurality of flash memory devices.

16. The method of claim 15 , wherein the at least one timing requirement is one of a maximum erase time, a maximum suspend erase time, a maximum write time, and a maximum read time.

17. The method of claim 10 , wherein the first command is a read command or a write command.

18. The method of claim 10 , wherein the data transfer rate for communications over the bus was assigned to the channel controller during initialization of the channel controller.

19. The method of claim 10 , wherein the data transfer rate for communications over the bus corresponds to a double data rate clock frequency.

Assignees

• Toshiba Memory Corp

Inventors

• Seo Kang Seok
• Jeong Hyoun Kwon
• Kim Jonghyeon

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F13/1626

  by reordering requests · CPC title

• G06F13/4234 Primary

  being a memory bus · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F13/4063

  Device-to-bus coupling · CPC title