Display

Patent metadata

Field	Value
Publication number	US-10528205-B2
Application number	US-201916239919-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Jun 18, 2014
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

To reduce disturbances in display of images due to static electricity without deteriorating optical properties in a display. The display includes a conductive pattern provided on the upper surface of the substrate, a protection layer provided on the upper surface of the substrate to cover the conductive pattern, and a conductive layer provided on the protection layer. The sheet resistance of the conductive pattern is not more than 8 Ω/square. A ratio of the total sum of areas of portions of the plurality of sub-pixels that overlap the conductive pattern in a plan view to the total sum of the areas of the plurality of sub-pixels is 1 to 22%. A sheet resistance of the conductive layer is higher than the sheet resistance of the conductive pattern.

First claim

What is claimed is:

1. A display comprising:
a substrate including a display region in which a plurality of pixels are arranged and a peripheral region around the display region;
a first conductive pattern including a plurality of touch electrodes having a plurality of bending parts and a plurality of dummy electrodes arranged between the touch electrodes in the display region on the substrate;
a second conductive pattern including a plurality of wirings in the peripheral region on the substrate, the plurality of wirings shaped so as to have a plurality of lines extending in a same direction as the first conductive pattern;
a protection layer covering the first conductive pattern and the second conductive pattern; and
a detection unit detecting input positions based on electrostatic capacities, wherein the first conductive pattern is made of one or more metals including at least one of aluminum (AI), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), or tungsten (W),
the plurality of touch electrodes are connected to the detection unit,
the plurality of dummy electrodes are not connected to the detection unit, and in a plan view, a ratio of an area of the second conductive pattern to an area of the peripheral region is larger than a ratio of an area of the first conductive pattern to an area of the display region.

2. The display according to claim 1 , wherein a specific resistance of the protection layer is higher than a specific resistance of the first and the second conductive patterns.

3. The display according to claim 1 , wherein the protection layer has a thickness which is larger than a thickness of the first conductive pattern.

4. The display according to claim 1 ,
wherein the plurality of touch electrodes are provided at intervals with respect to each other in the plan view, and
the detection unit detects input positions based on electrostatic capacities of each of the plurality of touch electrodes.

5. The display according to claim 1 , wherein a sheet resistance of the second conductive pattern is not more than 8 Ω/square.

6. The display according to claim 1 , further comprising:
a conductive layer on the protection layer;
a polarizing layer on the conductive layer,
wherein a sheet resistance of the conductive layer is higher than the sheet resistance of the second conductive pattern.

7. The display device according to claim 1 , wherein the first conductive pattern extends along a first length, and the plurality of lines extends along a second length that is substantially the same as the first length.

8. The display device according to claim 1 , wherein the plurality of touch electrodes extend along a first length, and the plurality of lines extends along a second length that is substantially the same as the first length.

Assignees

• Japan Display Inc

Inventors

• Ikeda Masanobu
• Ishizaki Koji
• Kurasawa Hayato
• Watanabe Yoshihiro
• Ishigaki Toshimasa
• Sonoda Daisuke
• Ide Tatsuya

Classifications

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• G02F1/136204

  Arrangements to prevent high voltage or static electricity failures · CPC title

• G02F2001/134372

  Physics · mapped topic

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title