Node unit including queuing engine for multicasting ethernet data and distributed antenna system including the same

Patent metadata

Field	Value
Publication number	US-10523452-B2
Application number	US-201515540638-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Dec 30, 2014
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Provided are a node unit including a queuing engine for multicasting Ethernet data, and a distributed antenna system including the same. The node unit is a node unit which is branch-connected to a plurality of lower nodes, and comprises: a media access control (MAC) module; and a queuing engine for interfacing Ethernet data between the MAC module and the plurality of branch-connected lower nodes, wherein the queuing engine multicasts Ethernet data received from the MAC module to the plurality of branch-connected lower nodes, transfers Ethernet data received from the plurality of branch-connected lower nodes to the MAC module, wherein the queuing engine comprises a buffer for buffering Ethernet data received from the plurality of branch-connected lower nodes, and outputting the buffered Ethernet data to the MAC module.

First claim

The invention claimed is:

1. A node unit connected to a plurality of lower node units, comprising:
a media access control (MAC) module;
a plurality of framers; and
a queuing engine for supporting Ethernet communication between the MAC module and the plurality of framers that respectively correspond to the plurality of lower node units,
wherein the queuing engine multicasts first Ethernet data received from the MAC module to the plurality of framers, transfers second Ethernet data received from the plurality of framers to the MAC module,
wherein the plurality of framers format the first Ethernet data according to a format for digital transmission, and format a digital signal received from the plurality of lower node units according to a format of the second Ethernet data, and
wherein the queuing engine comprises a buffer for buffering the second Ethernet data received from the plurality of framers, and outputting the buffered second Ethernet data to the MAC module.

2. The node unit of claim 1 , wherein the queuing engine is implemented within a field programmable gate array (FPGA) that constitutes a digital part of the node unit.

3. The node unit of claim 1 , wherein the buffer is a first-in first-out (FIFO) buffer.

4. The node unit of claim 3 , wherein the FIFO buffer has a size of twice or more a full frame length of the second Ethernet data.

5. The node unit of claim 1 , wherein at least one of the first Ethernet data and the second Ethernet data is control/management signals transmitted from an external management device connected to the node unit or transmitted to the external management device.

6. The node unit of claim 1 , wherein the queuing engine further comprises a signal control logic for determining that the first Ethernet data received from the MAC module is effective and for dropping the first Ethernet data when the first Ethernet data is determined to be non-effective.

7. The node unit of claim 1 , wherein the queuing engine further comprises a signal control logic for determining that the second Ethernet data received from the plurality of framers is effective and for dropping the second Ethernet data when the second Ethernet data is determined to be non-effective.

8. The node unit of claim 1 , wherein the queuing engine further comprises a scheduler for determining whether at least one the first Ethernet data and the second Ethernet data is effective, and for outputting at least one of the first Ethernet data and the second Ethernet data determined to be effective.

9. The node unit of claim 8 , wherein the scheduler determines that the first Ethernet data received from the MAC module is effective, and drops the first Ethernet data when the first Ethernet data is determined to be non-effective.

10. The node unit of claim 8 , wherein the scheduler determines that the second Ethernet data received from the plurality of framers is effective and drops the second Ethernet data when the second Ethernet data is determined to be non-effective.

11. A node unit cascade-connected to an upper node unit and a lower node unit, comprising:
a media access control (MAC) module;
a first framer;
a second framer; and
a queuing engine for supporting Ethernet communication among the MAC module, the first framer corresponding to the upper node unit and the second framer corresponding to the lower node unit,
wherein the queuing engine multicasts third Ethernet data received from the first framer to the MAC module and the second framer, multicasts fourth Ethernet data received from the second framer to the MAC module and the first framer, multicasts fifth Ethernet data received from the MAC module to the first framer and the second framer,
wherein the first framer formats the fourth Ethernet data or the fifth Ethernet data according to a format for digital transmission, and formats a first digital signal received from the upper node unit according to a format of the third Ethernet data,
wherein the second framer formats the third Ethernet data or the fifth Ethernet data according to the format for digital transmission, and formats a second digital signal received from the lower node unit according to a format of the fourth Ethernet data, and
wherein the queuing engine comprises:
a first buffer for buffering the third Ethernet data received from the first framer or the fourth Ethernet data received from the second framer, and outputting the buffered third Ethernet data or the buffered fourth Ethernet data to the MAC module;
a second buffer for buffering the third Ethernet data received from the first framer or the fifth Ethernet data received from the MAC module, and outputting the buffered third Ethernet data or the buffered fifth Ethernet Data to the second framer; and
a third buffer for buffering the fourth Ethernet data received from the second framer or the fifth Ethernet data received from the MAC module, and outputting the buffered fourth Ethernet data or the buffered fifth Ethernet data to the first framer.

12. The node unit of claim 11 , wherein the queuing engine is implemented within a field programmable gate array (FPGA) that constitutes a digital part of the node unit.

13. The node unit of claim 11 , wherein at least one of the first buffer, the second buffer, and the third buffer is a first-in first-out (FIFO) buffer.

14. The node unit of claim 13 , wherein the FIFO buffer has a size of twice or more a full frame length of at least one of the third Ethernet data, the fourth Ethernet data, and the fifth Ethernet data.

15. The node unit of claim 11 , wherein at least one of the third Ethernet data, the fourth Ethernet data, and the fifth Ethernet data is control/management signals transmitted from an external management device connected to the node unit or transmitted to the external management device.

16. The node unit of claim 11 , wherein the queuing engine further comprises a first scheduler for determining that the third Ethernet data input from the first buffer is effective, and outputting the third Ethernet data determined to be effective to the MAC module.

17. The node unit of claim 11 , wherein the queuing engine further comprises a second scheduler for determining that the fourth Ethernet data input from the second buffer is effective, and outputting the fourth Ethernet data determined to be effective to the second framer.

18. The node unit of claim 11 , wherein the queuing engine further comprises a third scheduler for determining whether the fifth Ethernet data input from the third buffer is effective, and outputting the fifth Ethernet data determined to be effective to the first framer.

Assignees

• Solid Inc

Inventors

• Kim Doyoon

Classifications

• H04L47/6245

  Modifications to standard FIFO or LIFO · CPC title

• H04L47/32

  by discarding or delaying data units, e.g. packets or frames · CPC title

• H04L45/66

  Layer 2 routing, e.g. in Ethernet based MAN's · CPC title

• H04L12/18 Primary

  for broadcast or conference {, e.g. multicast} · CPC title

• H04L49/90

  Buffering arrangements · CPC title