Distributed differential interconnect

Patent metadata

Field	Value
Publication number	US-10523272-B2
Application number	US-201715606820-A
Country	US
Kind code	B2
Filing date	May 26, 2017
Priority date	May 26, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

First claim

What is claimed is:

1. An electronic apparatus comprising:
a first endpoint having a first differential connection interface;
a second endpoint having a second differential connection interface; and
a differential interconnect coupled between the first differential connection interface and the second differential connection interface, the differential interconnect including:
a plus pathway extending between the first differential connection interface and the second differential connection interface, the plus pathway including multiple plus conductors; and
a minus pathway extending between the first differential connection interface and the second differential connection interface, the minus pathway including multiple minus conductors,
individual plus conductors of the multiple plus conductors disposed in an interleaved arrangement with individual minus conductors of the multiple minus conductors.

2. The electronic apparatus of claim 1 , wherein the individual plus conductors and the individual minus conductors are disposed in a substantially parallel arrangement.

3. The electronic apparatus of claim 1 , further comprising:
an integrated circuit that includes a substrate,
wherein the multiple plus conductors and the multiple minus conductors comprise metal lines in a metal layer of the substrate.

4. The electronic apparatus of claim 1 , further comprising:
a printed circuit board (PCB) that includes a substrate,
wherein the multiple plus conductors and the multiple minus conductors comprise metal traces on the substrate.

5. The electronic apparatus of claim 1 , wherein:
each of the multiple plus conductors and the multiple minus conductors include an input side and an output side;
the first differential connection interface comprises:
a plus input node coupled to the input side of each plus conductor of the multiple plus conductors; and
a minus input node coupled to the input side of each minus conductor of the multiple minus conductors; and
the second differential connection interface comprises:
a plus output node coupled to the output side of each plus conductor of the multiple plus conductors; and
a minus output node coupled to the output side of each minus conductor of the multiple minus conductors.

6. The electronic apparatus of claim 1 , further comprising a ground node.

7. The electronic apparatus of claim 6 , wherein the ground node comprises at least one of a ground plane or a ground pathway.

8. The electronic apparatus of claim 1 , wherein:
the first endpoint comprises a charge pump of a phase-locked loop; and
the second endpoint comprises a capacitor of the phase-locked loop.

9. The electronic apparatus of claim 8 , further comprising:
the phase-locked loop, the phase-locked loop comprising:
a phase frequency detector coupled to the charge pump;
the charge pump coupled to the capacitor via the differential interconnect;
a filter comprising the capacitor; and
a voltage-controlled oscillator (VCO) coupled between the filter and the phase frequency detector.

10. The electronic apparatus of claim 9 , wherein:
the voltage-controlled oscillator is configured to generate a signal as part of the phase-locked loop; and
the electronic apparatus is configured to provide the signal to one or more other components of the electronic apparatus to facilitate operation of the one or more other components responsive to the signal.

11. The electronic apparatus of claim 1 , wherein the first differential connection interface comprises a differential driver configured to drive a differential signal onto the differential interconnect.

12. The electronic apparatus of claim 11 , wherein:
the differential signal comprises a plus signal and a minus signal; and
the differential driver comprises:
a plus driver configured to drive the plus signal onto the plus pathway; and
a minus driver configured to drive the minus signal onto the minus pathway.

13. The electronic apparatus of claim 12 , wherein the plus signal and the minus signal comprise complementary signals that encode information relative to each other.

14. The electronic apparatus of claim 12 , wherein:
the plus driver is configured to distribute the plus signal across the multiple plus conductors of the plus pathway; and
the minus driver is configured to distribute the minus signal across the multiple minus conductors of the minus pathway.

15. The electronic apparatus of claim 12 , wherein:
the second differential connection interface comprises a differential receiver configured to receive the differential signal via the differential interconnect; and
the differential receiver comprises:
a plus receiver configured to receive the plus signal via the plus pathway; and
a minus receiver configured to receive the minus signal via the minus pathway.

16. An electronic apparatus comprising:
a first endpoint including a differential driver configured to drive a differential signal;
a second endpoint including a differential receiver configured to receive the differential signal; and
means for propagating the differential signal between the first endpoint and the second endpoint via multiple plus conductors and multiple minus conductors.

17. The electronic apparatus of claim 16 , wherein:
the differential signal comprises a plus signal and a minus signal that are complementary to each other; and
the differential driver comprises:
a plus driver configured to drive the plus signal using the means for propagating the differential signal; and
a minus driver configured to drive the minus signal using the means for propagating the differential signal.

18. The electronic apparatus of claim 16 , wherein:
the means for propagating the differential signal comprises a differential interconnect that is distributed across the multiple plus conductors and the multiple minus conductors; and
the multiple plus conductors are disposed in an interleaved arrangement with respect to the multiple minus conductors.

19. The electronic apparatus of claim 16 , wherein:
the means for propagating the differential signal includes multiple adjacent complementary conductors that each include a plus conductor of the multiple plus conductors and a minus conductor of the multiple minus conductors; and
the means for propagating the differential signal comprises means for generating magnetic flux that is additive in regions between adjacent complementary conductors of the multiple adjacent complementary conductors and subtractive beyond the regions between the adjacent complementary conductors.

20. An integrated circuit comprising:
a plus input node;
a minus input node;
a plus output node;
a minus output node; and
a differential interconnect including:
a first conductor having a plus polarity, the first conductor coupled between the plus input node and the plus output node;
a second conductor having a minus polarity, the second conductor coupled between the minus input node and the minus output node, the second conductor disposed adjacent to the first conductor;
a third conductor having the plus polarity, the third conductor coupled between the plus input node and the plus output node, the third conductor disposed adjacent to the second conductor; and
a fourth conductor having the minus polarity, the fourth conductor coupled between the minus input node and the minus output node, the fourth conductor disposed adjacent to the third conductor.

21. The integrated circuit of claim 20 , wherein the fir

Assignees

• Qualcomm Inc

Inventors

• Vallabhaneni Madhukar
• Koppassery Girish
• Chen Xinhua
• Zhuang Jingcheng

Classifications

• H01R12/00

  Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures (printed connections to, or between, printed circuits H05K1/11) · CPC title

• H04L25/0274

  Arrangements for ensuring balanced coupling · CPC title

• H01R9/11

  End pieces for multiconductor cables supported by the cable and for facilitating connections to other conductive members {, e.g. for liquid cooled welding cables} · CPC title

• H04L25/085

  Arrangements for reducing interference in line transmission systems, e.g. by differential transmission · CPC title

• H04L25/00

  Baseband systems · CPC title