Optically isolated latching solid state relay with low on resistance and linear operation

Patent metadata

Field	Value
Publication number	US-10523198-B1
Application number	US-201816104920-A
Country	US
Kind code	B1
Filing date	Aug 19, 2018
Priority date	Aug 19, 2018
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A latching relay includes a supply terminal, a load terminal, first and second coupling circuits, a latch circuit, first and second transistors, and a local supply node coupled to a capacitor. In one example, the supply terminal is coupled to a supply node and the load terminal is coupled to the load. The first and second transistors control the conductivity of a drive transistor coupled to the load. A microcontroller controls the latching relay to switch the load on and off. To enable the load, the microcontroller sinks current from the supply terminal and through the first coupling circuit. While the load is enabled, the capacitor is discharged. The latching relay is operable in a refresh mode in which current is pulsed through the first coupling circuit causing capacitor to be re-charged from the supply terminal. To disable the load, the microcontroller sinks current through the second coupling circuit.

First claim

What is claimed is:

1. A packaged electronic device comprising:
a supply terminal;
a load terminal;
a first coupling circuit;
a second coupling circuit;
a first transistor having a first terminal, a second terminal, and a third terminal;
a second transistor having a first terminal, a second terminal, and a third terminal, wherein the third terminal of the first transistor is coupled to the second terminal of the second transistor;
a latch circuit having a first terminal and a second terminal, wherein the first terminal of the latch circuit is coupled to the first coupling circuit, and wherein the second terminal of the latch circuit is coupled to the second coupling circuit, wherein the first coupling circuit is operable to configure the latch circuit such that the conductivities of the first transistor and the second transistor are switched thereby causing current to flow through a load coupled to the load terminal, and wherein the second coupling circuit is operable to configure the latch circuit such that the conductivities of the first transistor and the second transistor are switched thereby causing current to stop flowing through the load; and

a local supply node connected to the latch circuit, the first coupling circuit, and the second coupling circuit, wherein the second terminal of the first transistor is coupled to the local supply node, wherein the local supply node is supplied by a capacitor, and wherein the packaged electronic device is operable in a refresh mode such that the capacitor is charged while the load is enabled by pulsing current through the first coupling circuit.

2. The packaged electronic device of claim 1 , wherein the packaged electronic device does not include any silicon-controlled rectifier (SCR) devices or any mechanical relays, and wherein the latch circuit is coupled to the first coupling circuit via optical coupling, inductive coupling, or capacitive coupling.

3. The packaged electronic device of claim 1 , further comprising:
a storage terminal, wherein the packaged electronic device is configurable such that a capacitor is coupled to the storage terminal;
a first diode having a first terminal and a second terminal, wherein the first terminal of the first diode is coupled to the first coupling circuit, and wherein the second terminal of the first diode is coupled to the storage terminal;
a second diode having a first terminal and a second terminal, wherein the first terminal of the second diode is coupled to the load terminal; and
a regulator circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the regulator circuit is coupled to the storage terminal, wherein the first terminal of the regulator circuit is coupled to the second terminal of the first diode, wherein the second terminal of the regulator circuit is coupled to the second terminal of the second diode, and wherein the third terminal of the regulator circuit is coupled to a ground terminal of the packaged electronic device.

4. The packaged electronic device of claim 1 , wherein the packaged electronic device is a packaged optically isolated latching relay, and wherein the supply terminal and the load terminal are package terminals of the packaged optically isolated latching relay.

5. The packaged electronic device of claim 1 , wherein the latch circuit also has a third terminal and a fourth terminal, wherein the third terminal of the latch circuit is coupled to the first terminal of the first transistor via an inverter, and wherein the fourth terminal of the latch circuit is coupled to the first terminal of the second transistor.

6. The packaged electronic device of claim 1 , wherein the first coupling circuit comprises:
a light emitting diode having a first terminal and second terminal, wherein the first terminal of the light emitting diode is coupled to the supply terminal, and wherein the second terminal of the light emitting diode is coupled to a control terminal of the packaged electronic device; and
a photovoltaic stack and photo diode circuit.

7. The packaged electronic device of claim 1 , wherein the second coupling circuit comprises:
a light emitting diode having a first terminal and second terminal, wherein the second terminal of the light emitting diode is coupled to a control terminal of the packaged electronic device; and
a photo diode circuit.

8. A packaged electronic device comprising:
a supply terminal;
a load terminal;
a first coupling circuit;
a second coupling circuit;
a first transistor having a first terminal, a second terminal, and a third terminal;
a second transistor having a first terminal, a second terminal, and a third terminal, wherein the third terminal of the first transistor is coupled to the second terminal of the second transistor;
a latch circuit having a first terminal and a second terminal, wherein the first terminal of the latch circuit is coupled to the first coupling circuit, and wherein the second terminal of the latch circuit is coupled to the second coupling circuit, wherein the first coupling circuit is operable to configure the latch circuit such that the conductivities of the first transistor and the second transistor are switched thereby causing current to flow through a load coupled to the load terminal, and wherein the second coupling circuit is operable to configure the latch circuit such that the conductivities of the first transistor and the second transistor are switched thereby causing current to stop flowing through the load; and
a third transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the third transistor is coupled to the third terminal of the first transistor, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor, and wherein the second terminal of the third transistor is coupled to the load terminal.

9. A method comprising:
(a) coupling a load terminal of a latching relay to a load, wherein the load is supplied by a load supply, wherein the load supply charges a capacitor through the load via the load terminal, and wherein the capacitor is charged via the load terminal while the load remains in a disabled state;
(b) switching the load from the disabled state to the enabled state such that current flows from the load supply, through the load, through the latching relay, and to another terminal of the latching relay, wherein the capacitor supplies power to the latching relay while the load is in the enabled state;
(c) charging the capacitor by pulsing current through a supply terminal of the latching relay, wherein the capacitor is charged while the load is in the enabled state; and
(d) switching the load from the enabled state to the disabled state.

10. The method of claim 9 , wherein the switching of the load in (b) occurs in response to a first signal switching from a first digital logic level to a second digital logic level, wherein the first signal is present on a first terminal of the latching relay, wherein the switching of the load in (d) occurs in response to a second signal switching from a first digital logic level to a second digital logic level, and wherein the second signal is present on a second terminal of the latching relay.

11. The method of claim 9 , wherein the switching of (b) involves a first transistor switching from a first conductive state to a second conductive state and a second transistor switching from a second conductive state to a first conductive state, and wherein the switching of (d) involves the first transistor switching from the second conductive state to the first conductive state and the second transistor switching

Assignees

• Littelfuse Inc

Inventors

• Gambuzza Michael J
• Gude Eirik L

Classifications

• H03K17/785 Primary

  controlling field-effect transistor switches · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H03K2217/0081

  Power supply means, e.g. to the switch driver · CPC title

• H03K17/689 Primary

  with galvanic isolation between the control circuit and the output circuit (H03K17/78 takes precedence) · CPC title