Pulse density modulation adjustment

Patent metadata

Field	Value
Publication number	US-10523190-B2
Application number	US-201715824345-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Nov 28, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

First claim

What is claimed is:

1. A modulator, comprising:
a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and
a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, truncate or extend a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

2. The modulator of claim 1 , wherein the adjusted PDM stream has a higher resolution than the generated PDM bit stream.

3. The modulator of claim 1 , wherein the bit stream adjuster comprises a multi-phase Delay Locked Loop (DLL) configured to divide the PDM clock into the PDM multi-phase clock.

4. The modulator of claim 1 , wherein the bit stream adjuster comprises a multi-phase Phase Locked Loop (PLL) configured to divide the PDM clock into the PDM multi-phase clock.

5. The modulator of claim 1 , wherein the bit stream adjuster comprises a series of inverters configured to divide the PDM clock into the PDM multi-phase clock.

6. The modulator of claim 1 , wherein the bit stream adjuster comprises:
a multiplexer configured to output the selected PDM clock phase based on a PDM phase select signal; and
a sampler configured to sample the generated PDM bit stream at the selected PDM clock phase, and output the truncated or extended PDM bit stream.

7. The modulator of claim 1 , wherein the pulse density modulator comprises a memory configured to store the bit stream information.

8. The modulator of claim 1 , further comprising:
a memory configured to store the PDM clock phase to be selected.

9. The modulator of claim 8 , wherein the PDM clock phase to be selected is selected from the memory by a logic circuit.

10. The modulator of claim 1 , wherein the PDM clock phase to be selected is provided to the bit stream adjuster directly by a processor.

11. The modulator of claim 1 , wherein the PDM clock phase to be selected is provided to the bit stream adjuster by a software routine.

12. A circuit, comprising:
the modulator of claim 1 ; and
a Voltage Controlled Oscillator (VCO) configured to be controlled based on the adjusted PDM bit stream.

13. The circuit of claim 12 , further comprising:
a Low Pass Filter (LPF) configured to convert the adjusted PDM bit stream to an analog voltage for controlling the VCO.

14. A modulator, comprising:
a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and
a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream,
wherein the bit stream adjuster is configured to operate at a frequency that is less than or equal to a frequency of the pulse density modulator.

15. A modulation method, comprising:
generating, by a pulse density modulator, from bit stream information, a Pulse Density Modulation (PDM) bit stream based on a PDM clock;
dividing, by a bit stream adjuster, the PDM clock into a PDM multi-phase clock;
truncating or extending, by the bit stream adjuster, a duration of at least one pulse of the generated PDM bit stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM bit stream; and
outputting, by the bit stream adjuster, an adjusted PDM bit stream,
wherein the adjusted PDM bit stream has a higher resolution than the generated PDM bit stream.

16. The modulation method of claim 15 , further comprising:
outputting, by a multiplexer of the bit stream adjuster, the selected PDM clock phase based on a PDM phase select signal; and
sampling, by a sampler of the bit stream adjuster, the generated PDM bit stream at the selected PDM clock phase to produce the truncated or extended PDM bit stream.

17. The modulation method of claim 15 , wherein the bit stream adjuster operates at a frequency that is less than or equal to a frequency of the pulse density modulator.

Assignees

• Infineon Technologies Ag

Inventors

• Costa Pedro
• Dewan Ketan

Classifications

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03K7/04 Primary

  Position modulation, i.e. PPM · CPC title

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title