Circuit and method for protecting a voltage regulating circuit against electrostatic discharges

US10522999B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10522999-B2
Application numberUS-201715436186-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2017
Priority dateAug 4, 2016
Publication dateDec 31, 2019
Grant dateDec 31, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.

First claim

Opening claim text (preview).

The invention claimed is: 1. An integrated circuit, comprising: a first terminal and a second terminal configured to be coupled to an antenna, a rectification circuit having inputs coupled to the first and second terminals and having an output, a processing circuit coupled to said output, a voltage regulating circuit configured to regulate a voltage between the first and second terminals, wherein the voltage regulating circuit includes only one transistor, or a group of several transistors in parallel, connected between the first and second terminals, a protection circuit configured to protect the processing circuit in the event of an electrostatic discharge while the integrated circuit is not powered, wherein the protection circuit includes a protection device and a triggering circuit configured to trigger the protection device in the event of the electrostatic discharge, and a control circuit configured to make the voltage regulating circuit inactive during the event of the electrostatic discharge while the integrated circuit is not powered regardless of a direction of flow of a pulse between the first and second terminals resulting from said event of the electrostatic discharge, wherein the control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first through fourth transistors are connected in series between the first and the second terminals, the first transistor having a gate connected to the second terminal and an electrode connected to the first terminal, the second transistor and the third transistor having respective gates connected to the triggering circuit and a common electrode connected to the gate of the only one transistor, or group of several transistors in parallel, of the voltage regulating circuit, and the fourth transistor having a gate connected to the first terminal and an electrode connected to the second terminal. 2. The integrated circuit according to claim 1 , wherein the control circuit is connected to a gate of the only one transistor, or group of several transistors in parallel, of the voltage regulating circuit and is configured to: connect said gate to the second terminal when the flow of the pulse from said event of the electrostatic discharge is from the first terminal towards the second terminal, and connect said gate to the first terminal when the flow of the pulse from said event of the electrostatic discharge is from the second terminal towards the first terminal. 3. The integrated circuit according to claim 1 , further comprising: a comparison circuit configured to activate the voltage regulating circuit in response to a voltage surge at the first and second terminals, and a resistance connected in series between an output of the comparison circuit and the gate of the only one transistor, or group of several transistors in parallel, of the voltage regulating circuit. 4. A device, comprising: an integrated circuit, comprising: a first terminal and a second terminal, a rectification circuit having inputs coupled to the first and second terminals and having an output, a processing circuit coupled to said output, a voltage regulating circuit configured to regulate a voltage between the first and second terminals, wherein the voltage regulating circuit includes only one transistor, or a group of several transistors in parallel, connected between the first and second terminals, a protection circuit configured to protect the processing circuit in the event of an electrostatic discharge while the integrated circuit is not powered, and a control circuit configured to make the voltage regulating circuit inactive during the event of the electrostatic discharge while the integrated circuit is not powered regardless of a direction of flow of a pulse between the first and second terminals resulting from said event of the electrostatic discharge, wherein the control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first through fourth transistors are connected in series between the first and the second terminals, the first transistor having a gate connected to the second terminal and an electrode connected to the first terminal, the second transistor and the third transistor having respective gates connected to the triggering circuit and a common electrode connected to the gate of the only one transistor, or group of several transistors in parallel, of the voltage regulating circuit, and the fourth transistor having a gate connected to the first terminal and an electrode connected to the second terminal; and an antenna connected to the first terminal and to the second terminal. 5. The device according to claim 4 , wherein the device is one of a chip card, a radio-frequency identification badge or a wireless communication device. 6. An integrated circuit, comprising: a first terminal and a second terminal configured to be coupled to an antenna, a rectification circuit having inputs coupled to the first and second terminals and having an output, an overvoltage sensing circuit configured to detect an overvoltage condition at the output of the rectification circuit and assert a first control signal, a voltage regulating circuit coupled between the first and second terminals and having a first control terminal, said voltage regulating circuit activated in response to said first control signal received at the first control terminal to couple the first and second terminals to each other; an electrostatic discharge sensing circuit configured to detect a surge condition at the output of the rectification circuit and assert a second control signal; a discharge circuit coupled to the output of the rectification circuit and having a second control terminal, said discharge circuit activated in response to said second control signal received at the second control terminal, and a control circuit configured to deactivate the voltage regulating circuit in response to assertion of the second control signal, wherein the control circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first through fourth transistors are connected in series between the first and the second terminals, the first transistor having a gate connected to the second terminal and an electrode connected to the first terminal, the second transistor and the third transistor having respective gates connected to receive the second control signal and a common electrode connected to the first control terminal of the voltage regulating circuit, and the fourth transistor having a gate connected to the first terminal and an electrode connected to the second terminal. 7. The integrated circuit of claim 6 , wherein said voltage regulating circuit comprises only one transistor connected between the first and second terminals. 8. The integrated circuit of claim 7 , wherein said control circuit connects a gate terminal of said one transistor to the second terminal when the detected surge condition is due to a flow of the electrostatic discharge from the first terminal towards the second terminal. 9. The integrated circuit of claim 7 , wherein said control circuit connects a gate terminal of said one transistor to the first terminal when the detected surge condition is due to a flow of the electrostatic discharge from the second terminal towards the first terminal. 10. The integrated circuit of claim 6 , wherein said voltage regulating circuit comprises a group of several transistors connected in parallel with each other between the first and second terminals. 11. The integrated circuit of claim 10 , wherein said con

Assignees

Inventors

Classifications

  • the record carrier comprising means for protecting against electrostatic discharge · CPC title

  • responsive to excess voltage appearing at terminals of integrated circuits · CPC title

  • using a short-circuiting device · CPC title

  • at least one of the integrated circuit chips comprising an arrangement for power management · CPC title

  • for electronic equipment (for converters H02H7/10; for electric measuring instruments G01R1/36; for DC voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08) · CPC title

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What does patent US10522999B2 cover?
An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the firs…
Who is the assignee on this patent?
St Microelectronics Rousset
What technology area does this patent fall under?
Primary CPC classification H02H7/1252. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).