Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10522685-B2
Application number	US-201816106625-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Dec 11, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises:
a semiconductor substrate;
a semiconductor fin positioned on the semiconductor substrate; and
a pseudo gate structure positioned on the semiconductor fin;
wherein the pseudo gate structure comprises a gate dielectric layer on a part of a surface of the semiconductor fin and a semiconductor layer on the gate dielectric layer; and
wherein the semiconductor layer comprises a dopant, wherein a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin;
forming a spacer layer on each side surface of two sides of the semiconductor layer;
forming an inter-layer dielectric layer surrounding the spacer layer and the pseudo gate structure, wherein an upper surface of the semiconductor layer is exposed on the inter-layer dielectric layer;
partially etching the semiconductor layer to remove a part of the semiconductor layer to form an opening on which the gate dielectric layer is exposed, wherein a remaining part of the semiconductor layer is on a side surface of the spacer layer; and
filling the opening with a metal gate layer.

2. The method according to claim 1 , wherein:
the conductivity type of the semiconductor fin is N-type, the conductivity type of the dopant is P-type, and the dopant comprises boron; or
the conductivity type of the semiconductor fin is P-type, the conductivity type of the dopant is N-type, and the dopant comprises phosphorus or arsenic.

3. The method according to claim 1 , wherein a doping density of the dopant ranges from 1×10 20 atoms/cm 3 to 1×10 21 atoms/cm 3 .

4. The method according to claim 1 , wherein the remaining part of the semiconductor layer is located on each side surface of two sides of the metal gate layer.

5. The method according to claim 1 , wherein a material of the semiconductor layer comprises polysilicon or amorphous silicon.

6. The method according to claim 5 , wherein the method further comprises:
before filling the opening with a metal gate layer, metalizing the remaining part of the semiconductor layer to form a metal silicide layer.

7. The method according to claim 6 , wherein a material of the metal silicide layer comprises nickel silicide (NiSi).

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg International Beijing Corp
• Semiconductor Mfg International Shanghai Corp

Inventors

• Zhao Meng

Classifications

• H10D64/01322

  the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps · CPC title

• H01L29/6653

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/812

  Electricity · mapped topic