Semiconductor structure, manufacturing method therefor, and high-k metal gate fin field-effect transistor

Patent metadata

Field	Value
Publication number	US-10522684-B2
Application number	US-201816039085-A
Country	US
Kind code	B2
Filing date	Jul 18, 2018
Priority date	Jul 27, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

This disclosure relates to a semiconductor structure for, e.g., a high-k metal gate fin field-effect transistor, and a manufacturing method therefor. The method may include providing a substrate structure including a first portion for forming a first PMOS device and a second portion for forming a second PMOS device; forming a first P-type work function adjustment layer on the substrate structure; forming a protective layer on the first P-type work function adjustment layer; patterning the protective layer to expose the first P-type work function adjustment layer on the first portion; oxidizing the exposed first P-type work function adjustment layer on the first portion; removing the protective layer; and forming a second P-type work function adjustment layer on the first P-type work function adjustment layer. Because the first P-type work function adjustment layer on the first portion is oxidized, gate voltage thresholds of the first portion and the second portion are different even when the thicknesses of metal layers on the first portion and the second portion are the same.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate structure comprising a first portion for forming a first PMOS device and a second portion for forming a second PMOS device;
forming a first P-type work function adjustment layer on the substrate structure;
forming a protective layer on the first P-type work function adjustment layer;
patterning the protective layer to expose the first P-type work function adjustment layer on the first portion;
oxidizing the exposed first P-type work function adjustment layer on the first portion;
removing the protective layer; and
forming a second P-type work function adjustment layer on the first P-type work function adjustment layer.

2. The manufacturing method according to claim 1 , wherein the substrate structure further comprises a third portion for forming a first NMOS device and a fourth portion for forming a second NMOS device, wherein the third portion and the fourth portion are covered sequentially by the same first P-type work function adjustment layer and the same second P-type work function adjustment layer as the first portion, and wherein the manufacturing method further comprises:
removing the second P-type work function adjustment layer on the third portion;
forming a third P-type work function adjustment layer on the second P-type work function adjustment layer of the first portion, second portion, and fourth portion, and on the first P-type work function adjustment layer of the third portion; and
removing the second P-type work function adjustment layer and the third P-type work function adjustment layer from the fourth portion.

3. The manufacturing method according to claim 2 , further comprising:
forming an N-type work function adjustment layer on the third P-type work function adjustment layer of the first portion, the second portion, and the third portion, and on the first P-type work function adjustment layer over the fourth portion.

4. The manufacturing method according to claim 3 , further comprising:
forming a barrier layer on the N-type work function adjustment layer over all portions.

5. The manufacturing method according to claim 3 , wherein the N-type work function adjustment layer comprises at least one of TiAl, TiAlC, TaAlN, TiAlN, TaCN, or AlN.

6. The manufacturing method according to claim 2 , wherein:
the first P-type work function adjustment layer, the second P-type work function adjustment layer, and the third P-type work function adjustment layer each comprise at least one of Ta, TiN, TaN, TaSiN, or TiSiN; and
the protective layer comprises at least one of amorphous silicon, polysilicon, silicon nitride, or silicon oxide.

7. The manufacturing method according to claim 1 , wherein the method further comprises performing an annealing processing before patterning the protective layer.

8. The manufacturing method according to claim 1 , wherein the substrate structure comprises:
an interface layer on a substrate; and
a high-dielectric-constant material layer on the interface layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg International Shanghai Corp
• Semiconductor Mfg International Beijing Corp

Inventors

• He Xin

Classifications

• H10P14/203

  using transformation of metal, e.g. oxidation or nitridation · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H01L29/785 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L21/76829

  Electricity · mapped topic