Semiconductor circuit using positive feedback field effect transistor for emulating neuron firing process

Patent metadata

Field	Value
Publication number	US-10522665-B2
Application number	US-201816007120-A
Country	US
Kind code	B2
Filing date	Jun 13, 2018
Priority date	Jun 22, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Semiconductor circuits are provided for emulating neuron firing process using a positive feedback transistor having first and second gate electrodes in the longitudinal direction of a channel region. The first gate electrode is connected to a gate electrode of a first p-channel MOSFET to be an input terminal and the second gate electrode is connected to a drain to be applied with a supply voltage. Thus electrons and holes can accumulate separately in a channel region (i.e., a body) under each of the gate electrodes by applying input signals to the input terminal and drastically reduce the wasted power consumption in the non-fired neurons because the current is turned on and off only at a moment that corresponds to a firing of the neuron. Thus, the semiconductor circuits can be driven by low power and have the same level of endurance as a general MOSFET.

First claim

What is claimed is:

1. A semiconductor circuit for emulating neuron firing process comprising:
a positive feedback transistor and a first n-channel MOSFET connected in parallel between a ground and a first node;
a first p-channel MOSFET connected between the first node and an electric power supply line; and
an inverter connected between the first node and an output terminal, wherein
a first gate electrode of the positive feedback transistor is connected to a pate electrode of the first p-channel MOSFET to be an input terminal,
a second gate electrode of the positive feedback transistor is connected to the first node to apply the supply voltage of the electric power supply line, and
an input voltage is applied between the electric power supply line and the input terminal, and the output terminal is connected to a gate electrode of the first n-channel MOSFET.

2. The semiconductor circuit of claim 1 , wherein the positive feedback transistor has source and drain regions formed of a different conductivity type with a channel region therebetween in a semiconductor substrate, and the first and second gate electrodes are configured in the longitudinal direction of the channel region near to the source and drain regions, respectively, on a gate insulator.

3. The semiconductor circuit of claim 2 , wherein the source region is n-type, the drain region is p-type, the channel region are p-type and intrinsic under the first and second gate electrodes, respectively, and the positive feedback transistor has a doping structure of P+IPN+ from the drain region.

4. A semiconductor circuit for emulating neuron firing process comprising:
a positive feedback transistor and a first n-channel MOSFET connected in parallel between a ground and a first node;
a first p-channel MOSFET connected between the first node and an electric power supply line; and
an inverter connected between the first node and an output terminal, wherein
a first gate electrode of the positive feedback transistor is connected to a pate electrode of the first p-channel MOSFET to be an input terminal,
a second gate electrode of the positive feedback transistor is connected to the first node to apply the supply voltage of the electric power supply line,
a gate electrode of the first n-channel MOSFET is connected to the input terminal,
a second p-channel MOSFET is connected between the electric power supply line and the input terminal,
a gate electrode of the second p-channel MOSFET is connected to the first node, a second n-channel MOSFET is connected between the input terminal and the ground, and
a gate electrode of the second n-channel MOSFET is connected to the output terminal.

5. The semiconductor circuit of claim 4 , wherein an input current is applied between the electric power supply line and the input terminal, and a capacitor and a resister are connected in parallel between the input terminal and the ground.

6. The semiconductor circuit of claim 5 , wherein the positive feedback transistor has source and drain regions formed of a different conductivity type with a channel region therebetween in a semiconductor substrate, and the first and second gate electrodes are configured in the longitudinal direction of the channel region near to the source and drain regions, respectively, on a gate insulator.

7. The semiconductor circuit of claim 6 , wherein the source region is n-type, the drain region is p-type, the channel region are p-type and intrinsic under the first and second gate electrodes, respectively, and the positive feedback transistor has a doping structure of P+IPN+ from the drain region.

8. The semiconductor circuit of claim 4 , wherein the positive feedback transistor has source and drain regions formed of a different conductivity type with a channel region therebetween in a semiconductor substrate, and the first and second gate electrodes are configured in the longitudinal direction of the channel region near to the source and drain regions, respectively, on a gate insulator.

9. The semiconductor circuit of claim 8 , wherein the source region is n-type, the drain region is p-type, the channel region are p-type and intrinsic under the first and second gate electrodes, respectively, and the positive feedback transistor has a doping structure of P+IPN+ from the drain region.

10. A semiconductor circuit for emulating neuron firing process comprising:
a positive feedback transistor and a first n-channel MOSFET connected in parallel between a ground and a first node;
a first p-channel MOSFET connected between the first node and an electric power supply line; and
an inverter connected between the first node and an output terminal, wherein
a first gate electrode of the positive feedback transistor is connected to a gate electrode of the first p-channel MOSFET to be an input terminal,
a second gate electrode of the positive feedback transistor is connected to the first node to apply the supply voltage of the electric power supply line,
the positive feedback transistor has source and drain regions formed of a different conductivity type with a channel region therebetween in a semiconductor substrate, and
the first and second gate electrodes are configured in the longitudinal direction of the channel region near to the source and drain regions, respectively, on a gate insulator.

11. The semiconductor circuit of claim 10 , wherein the source region is n-type, the drain region is p-type, the channel region are p-type and intrinsic under the first and second gate electrodes, respectively, and the positive feedback transistor has a doping structure of P+IPN+ from the drain region.

Assignees

• Seoul Nat Univ R&Db Foundation

Inventors

• Park Byung-Gook
• Kwon Min-Woo
• Hwang Sungmin
• Baek Myung-Hyun
• Jang Tae-Jin

Classifications

• G06N3/065

  Analogue means · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title

• G06N3/10

  Interfaces, programming languages or software development kits, e.g. for simulating neural networks · CPC title

• H01L29/4238

  Electricity · mapped topic