Memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10522595-B2
Application number	US-201615334750-A
Country	US
Kind code	B2
Filing date	Oct 26, 2016
Priority date	Oct 27, 2015
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A semiconductor device includes: a first memory cell, a bit line and a second memory cell. The first memory cell has a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device. The bit line is on the first memory cell. The second memory cell is on the bit line, and has a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode. The first and second stack structures are symmetrical with respect to the bit line.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of lower word lines on a substrate, the plurality of lower word lines extending in a first direction parallel to a top surface of the substrate;
a plurality of common bit lines on the plurality of lower word lines, the plurality of common bit lines extending in a second direction parallel to the top surface of the substrate, the second direction different from the first direction;
a plurality of upper word lines on the plurality of common bit lines, the plurality of upper word lines extending in the first direction;
a plurality of first memory cell structures at intersections between the plurality of lower word lines and the plurality of common bit lines, each of the plurality of first memory cell structures including a first memory layer and a first selection device, the first selection device having ovonic threshold switching (OTS) characteristics; and
a plurality of second memory cell structures at intersections between the plurality of upper word lines and the plurality of common bit lines, each of the plurality of second memory cell structures including a second memory layer and a second selection device, the second selection device having OTS characteristics, wherein
the plurality of first memory cell structures have structures symmetrical to structures of the plurality of second memory cell structures with respect to the plurality of common bit lines in a third direction,
the third direction perpendicular to the first direction,
the first and second memory layers are configured to store data, and
a sidewall of a first of the plurality of first memory cell structures, a sidewall of a first of the second memory cell structures, and a sidewall of a first of the plurality of common bit lines are self-aligned.

2. The memory device of claim 1 , wherein
each of the plurality of first memory cell structures further includes a first heater electrode;
the first memory layer is between the first heater electrode and the first selection device;
each of the plurality of second memory cell structures further includes a second heater electrode; and
the second memory layer is between the second heater electrode and the second selection device.

3. The memory device of claim 2 , wherein
the first heater electrode does not contact the first selection device; and
the second heater electrode does not contact the second selection device.

4. A memory device comprising:
a plurality of first lower word lines on a substrate, the plurality of first lower word lines extending in a first direction parallel to a top surface of the substrate;
a plurality of first common bit lines on the plurality of first lower word lines, the plurality of first common bit lines extending in a second direction parallel to the top surface of the substrate, the second direction different from the first direction;
a plurality of first upper word lines on the plurality of first common bit lines, the plurality of first upper word lines extending in the first direction;
a plurality of first memory cell structures at intersections between the plurality of first lower word lines and the plurality of first common bit lines, each of the plurality of first memory cell structures including a first memory layer and a first selection device, the first selection device having ovonic threshold switching (OTS) characteristics; and
a plurality of second memory cell structures at intersections between the plurality of first upper word lines and the plurality of first common bit lines, each of the plurality of second memory cell structures including a second memory layer and a second selection device, the second selection device having OTS characteristics, wherein
the plurality of first memory cell structures have structures symmetrical to structures of the plurality of second memory cell structures with respect to the plurality of first common bit lines in a third direction,
the third direction is perpendicular to the first direction,
the first and second memory layers are configured to store data,
a first sidewall of a first of the plurality of first memory cell structures, a first sidewall of a first of the plurality of second memory cell structures and a first longitudinal sidewall of a first of the plurality of first common bit lines are self-aligned, and
a second sidewall of the first of the plurality of first memory cell structures is aligned with a longitudinal sidewall of a first of the plurality of first lower word lines.

5. The memory device of claim 4 , wherein
a first sidewall of a first selection device among the first selection devices is aligned with a longitudinal sidewall of a first of the plurality of first lower word lines; and
a second sidewall of the first selection device among the first selection devices is aligned with a longitudinal sidewall of a first of the plurality of first common bit lines.

6. The memory device of claim 4 , wherein
a first sidewall of a second selection device among the second selection devices is aligned with a longitudinal sidewall of a first of the plurality of first upper word lines; and
a second sidewall of the second selection device among the second selection devices is aligned with a longitudinal sidewall of a first of the plurality of first common bit lines.

7. The memory device of claim 4 , wherein
each of the plurality of first memory cell structures further includes a first heater electrode;
the first memory layer is between the first heater electrode and the first selection device;
each of the plurality of second memory cell structures further includes a second heater electrode; and
the second memory layer is between the second heater electrode and the second selection device.

8. The memory device of claim 4 , further comprising:
a plurality of second lower word lines on the plurality of first upper word lines, the plurality of second lower word lines extending in the first direction;
a plurality of second common bit lines on the plurality of second lower word lines, the plurality of second common bit lines extending in the second direction;
a plurality of second upper word lines on the plurality of second common bit lines, the plurality of second upper word lines extending in the first direction;
a plurality of third memory cell structures at intersections between the plurality of second lower word lines and the plurality of second common bit lines, each of the plurality of third memory cell structures having a third memory layer and a third selection device, the third selection device having OTS characteristics; and
a plurality of fourth memory cell structures at intersections between the plurality of second upper word lines and the plurality of second common bit lines, each of the plurality of fourth memory cell structures including a fourth memory layer and a fourth selection device, the fourth selection device having OTS characteristics.

9. A semiconductor device comprising:
a first memory cell having a first stack structure including a first memory layer between a first heater electrode and a first ovonic threshold switching device;
a bit line on the first memory cell; and
a second memory cell on the bit line, the second memory cell having a second stack structure including a second memory layer between a second ovonic threshold switching device and a second heater electrode, the first and second stack structures being symmetrical with respect to the bit line,
wherein a sidewall of the first memory cell, the second memory cell structures, and the bit line is self-aligned, and
the first and second memory layers are configured to store data.

10. The semiconductor device of claim 9 , wherein

Assignees

• Samsung Electronics Co Ltd

Inventors

• Terai Masayuki

Classifications

• H01L45/143

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/126

  Electricity · mapped topic