Method for manufacturing CMOS image sensor

US10522585B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10522585-B2
Application numberUS-201715488658-A
CountryUS
Kind codeB2
Filing dateApr 17, 2017
Priority dateApr 17, 2017
Publication dateDec 31, 2019
Grant dateDec 31, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a substrate having a first surface and a second surface opposite to each other; a conductive layer disposed on the first surface of the substrate; a transparent silicon dioxide layer disposed on the conductive layer; a transparent undoped silicon glass layer disposed on the transparent silicon dioxide layer, wherein the substrate has an etch selectivity with respect to the transparent undoped silicon glass; a carrier; and a device layer including a plurality of image sensors and disposed between the carrier and the second surface of the substrate. 2. The semiconductor device of claim 1 , wherein the etch selectivity is substantially greater than 3. 3. The semiconductor device of claim 1 , wherein a thickness of the transparent undoped silicon glass layer substantially ranges from 1000 angstrom to 2000 angstrom. 4. The semiconductor device of claim 1 , wherein a reflective index of the transparent undoped silicon glass layer is substantially equal to or smaller than 1.46. 5. The semiconductor device of claim 1 , wherein the image sensors are near-infrared image sensors. 6. A method for manufacturing a semiconductor device, the method comprising: providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, and providing the substrate comprises bonding the second surface to a carrier; forming a device layer including a plurality of image sensors over the substrate; forming a conductive layer on the first surface of the substrate; forming a transparent layer on the conductive layer; forming a transparent hard mask layer on the transparent layer; forming a patterned etch mask layer on a plurality of first portions of the transparent hard mask layer, wherein a plurality of second portions of the transparent hard mask layer are exposed; and performing an etch process through the patterned etch mask layer to remove the second portions of the transparent hard mask layer, a plurality of portions of the transparent layer, a plurality of portions of the conductive layer, and a plurality of portions of the substrate, wherein the portions of the substrate are removed from the first surface to the second surface of the substrate, and the patterned etch mask layer is consumed by an etchant of the etch process to expose the first portions of the transparent hard mask layer during removing the portions of the substrate. 7. The method of claim 6 , wherein the device layer is formed on the second surface of the substrate, bonding the second surface to the carrier comprises bonding the device layer on the second surface to the device layer, and performing the etch process comprises exposing portions of the device layer. 8. The method of claim 7 , wherein the device layer is formed to comprise a plurality of near-infrared image sensors. 9. The method of claim 6 , wherein the substrate comprises silicon, the transparent layer comprises silicon dioxide, and the transparent hard mask layer comprises undoped silicon glass. 10. The method of claim 6 , wherein a ratio of an etch rate of the substrate relative to an etch rate of the transparent hard mask layer is substantially greater than 3, and the transparent hard mask layer is formed to have a thickness which is greater than 3000 angstrom. 11. The method of claim 6 , wherein forming the transparent hard mask layer is performed after the second surface of the substrate is bonded to the carrier. 12. The method of claim 6 , wherein forming the transparent hard mask layer is performed before the second surface of the substrate is bonded to the carrier. 13. The method of claim 6 , wherein performing the etch process comprises: etching the second portions of the transparent hard mask layer and the portions of the transparent layer through the patterned etch mask layer; etching the portions of the conductive layer through the patterned etch mask layer and the transparent hard mask layer; and etching the portions of the substrate through the patterned etch mask layer and the transparent hard mask layer. 14. A method for manufacturing a semiconductor device, the method comprising: providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other; forming a device layer that includes a plurality of image sensors on the second surface of the substrate; forming a conductive layer on the first surface of the substrate; forming a transparent layer on the conductive layer; forming a transparent hard mask layer on the transparent layer; bonding the device layer to a carrier; forming a patterned etch mask layer on a plurality of portions of the transparent hard mask layer; etching the transparent hard mask layer and the transparent layer through the patterned etch mask layer; and etching the conductive layer and the substrate through the patterned etch mask layer and the transparent hard mask layer to expose a plurality of portions of the device layer, wherein an etch rate of the substrate is greater than an etch rate of the transparent hard mask layer, and the patterned etch mask layer is removed after etching the conductive layer and before etching the substrate is complete. 15. The method of claim 14 , wherein the device layer is formed to comprise a plurality of near-infrared image sensors. 16. The method of claim 14 , wherein the substrate comprises silicon, the transparent layer comprises silicon dioxide, and the transparent hard mask layer comprises undoped silicon glass. 17. The method of claim 14 , wherein a ratio of the etch rate of the substrate relative to the etch rate of the transparent hard mask layer is substantially greater than 3, and the transparent hard mask layer is formed to have a thickness which is greater than 3000 angstrom. 18. The method of claim 14 , wherein forming the transparent hard mask layer is performed after the device layer is bonded to the carrier. 19. The method of claim 14 , wherein forming the transparent hard mask layer is performed before the device layer is bonded to the carrier. 20. The semiconductor device of claim 1 , wherein the transparent undoped silicon glass layer is in contact with the transparent silicon dioxide layer.

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What does patent US10522585B2 cover?
A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disp…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/14685. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).