Computer modules with small thicknesses and associated methods of manufacturing

Patent metadata

Field	Value
Publication number	US-10522515-B2
Application number	US-201916285081-A
Country	US
Kind code	B2
Filing date	Feb 25, 2019
Priority date	Jan 14, 2009
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

First claim

We claim:

1. A computer module, comprising:
a module substrate having a first side, a second side opposite the first side, an aperture extending between the first and second sides, a first plurality of bond sites adjacent to the aperture, and a second plurality of bond sites along an outer edge of the module substrate operably connected to the first plurality of bond sites and configured to electrically couple with a computer socket; and
a microelectronic package including a stack of semiconductor dies and a package substrate carrying the stack of semiconductor dies, the package substrate having a plurality of contact pads corresponding to and electrically coupled to the first plurality of bond sites adjacent the aperture of the module substrate, wherein at least a portion of the stack of semiconductor dies is inside the aperture, and wherein the stack of semiconductor dies includes at least a memory controller die and a memory die, each of the memory die and the memory controller die being electrically coupled with the second plurality of bond sites through the first plurality of bond sites.

2. The computer module of claim 1 wherein the microelectronic package includes an encapsulant at least partially encapsulating the stack of semiconductor dies, and wherein the aperture has a cross-sectional dimension larger than that of the encapsulant.

3. The computer module of claim 1 wherein the aperture has a cross-sectional dimension larger than a cross-sectional dimension of the stack of semiconductor dies and smaller than a cross-sectional dimension of the package substrate.

4. The computer module of claim 1 wherein the plurality of contact pads is disposed adjacent a peripheral edge of the package substrate.

5. The computer module of claim 1 wherein the package substrate has a thickness less than a depth of the recess.

6. The computer module of claim 1 wherein the package substrate has a thickness greater than or equal to a depth of the recess.

7. The computer module of claim 1 wherein the plurality of contact pads is electrically coupled to the first plurality of bond sites by a corresponding plurality of electric couplers.

8. A computer module, comprising:
a module substrate having a module material and an aperture extending at least partially into the module material, a first plurality of bond sites adjacent to the aperture, and a second plurality of bond sites along an outer edge of the module substrate operably connected to the first plurality of bond sites adjacent to the aperture and configured to electrically couple with a computer socket; and
a microelectronic package having a stack of semiconductor dies and a package substrate carrying the stack of semiconductor dies, the package substrate having a plurality of contact pads corresponding to and electrically coupled to the first plurality of bond sites adjacent to the aperture, wherein at least a portion of the stack of semiconductor dies is inside the aperture, and wherein the stack of semiconductor dies includes at least a memory controller die and a memory die, each of the memory die and the memory controller die being electrically coupled with the second plurality of bond sites through the first plurality of bond sites.

9. The computer module of claim 8 wherein the microelectronic package includes an encapsulant at least partially encapsulating the stack of semiconductor dies, and wherein the aperture has a cross-sectional dimension larger than that of the encapsulant.

10. The computer module of claim 8 wherein the aperture has a cross-sectional dimension larger than a cross-sectional dimension of the stack of semiconductor dies and smaller than a cross-sectional dimension of the package substrate.

11. The computer module of claim 8 wherein the plurality of contact pads is disposed adjacent a peripheral edge of the package substrate.

12. The computer module of claim 8 wherein the package substrate has a thickness less than a depth of the recess.

13. The computer module of claim 8 wherein the package substrate has a thickness greater than or equal to a depth of the recess.

14. The computer module of claim 8 wherein the plurality of contact pads is electrically coupled to the first plurality of bond sites by a corresponding plurality of electric couplers.

15. A computer module, comprising:
a module substrate having a first side, a second side opposite the first side, an aperture extending between the first and second sides, a first plurality of bond sites adjacent to the aperture at the first side, a second plurality of bond sites adjacent to the aperture at the second side, and a third plurality of bond sites along an outer edge of the module substrate operably connected to the first and second pluralities of bond sites and configured to electrically couple with a computer socket;
a first microelectronic package having a first stack of semiconductor dies and a first package substrate carrying the first stack of semiconductor dies, the first package substrate having a first plurality of contact pads corresponding to and electrically coupled to the first plurality of bond sites adjacent to the aperture at the first side, wherein at least a portion of the first stack of semiconductor dies is inside the aperture, and wherein the first stack of semiconductor dies includes at least a first memory controller die and a first memory die, each of the first memory die and the first memory controller die being electrically coupled with the third plurality of bond sites through the first plurality of bond sites; and
a second microelectronic package having a second stack of semiconductor dies and a second package substrate carrying the second stack of semiconductor dies, the second package substrate having a second plurality of contact pads corresponding to and aligned with the second plurality of bond sites adjacent to the aperture at the second side, wherein at least a portion of the second stack of semiconductor dies is inside the aperture, and wherein the second stack of semiconductor dies includes at least a second memory controller die and a second memory die, each of the second memory die and the second memory controller die being electrically coupled with the third plurality of bond sites through the second plurality of bond sites.

Assignees

• Micron Technology Inc

Inventors

• Gibbons Kevin
• Reynolds Tracy V
• Corisis David J

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title