High-speed semiconductor modules

Patent metadata

Field	Value
Publication number	US-10522506-B2
Application number	US-201615264579-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Dec 17, 2015
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.

First claim

What is claimed is:

1. A semiconductor module, comprising:
a module substrate with an electric connection element;
at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips, wherein the at least one semiconductor package further comprises a plurality of through electrodes electrically connecting the plurality of semiconductor chips to a package substrate of the semiconductor package and penetrating at least a portion of the plurality of semiconductor chips, respectively; and
a connection region electrically connecting the semiconductor package to the module substrate,
wherein the connection region comprises:
a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the electric connection element;
a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the electric connection element; and
a third region electrically connected to command/address signal terminals of both the first and second chips of the semiconductor package,
wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.

2. The semiconductor module of claim 1 , wherein:
the semiconductor package comprises a package substrate having a bottom surface and a top surface opposite to each other, the bottom surface facing the module substrate;
the semiconductor chips are provided on the top surface of the package substrate and are arranged so as to be adjacent to one another in a first direction parallel to the top surface of the package substrate; and
the first direction extends away from the electric connection element of the module substrate.

3. The semiconductor module of claim 2 , wherein:
the connection region is provided on the bottom surface of the package substrate; and the first and third regions of the connection region are arranged so as to be adjacent to one another in the first direction.

4. The semiconductor module of claim 3 , wherein the first and second regions are arranged so as to be adjacent to one another in a second direction perpendicular to the first direction.

5. The semiconductor module of claim 1 , wherein the semiconductor package further comprises a plurality of connection terminals that electrically connect the semiconductor chips to a package substrate of the semiconductor package and are provided between the through electrodes of the semiconductor chips.

6. The semiconductor module of claim 1 , wherein:
the module substrate comprises a top surface and a bottom surface opposite to each other;
the semiconductor package is a first semiconductor package of a plurality of semiconductor packages; and
the semiconductor packages are provided on both the top and bottom surfaces.

7. The semiconductor module of claim 1 , wherein:
the first region comprises a plurality of first connection elements;
the second region comprises a plurality of second connection elements; and
the plurality of first connection elements are interleaved with the plurality of second connection elements.

8. The semiconductor module of claim 1 , wherein:
the semiconductor package comprises a package substrate having a bottom surface and a top surface opposite to each other, the bottom surface facing the module substrate;
the semiconductor chips are provided on the top surface of the package substrate and arranged so as to be adjacent to each other in a first direction parallel to the top surface of the package substrate; and
the first direction extends in parallel with the electric connection element of the module substrate.

9. A semiconductor module, comprising:
a module substrate having a top surface and a bottom surface opposite the top surface;
a plurality of semiconductor packages on the top surface of the module substrate, the plurality of semiconductor packages being arranged so as to be adjacent to each other in a first direction;
an electric connection element on the module substrate and extending in the first direction;
wherein each of the semiconductor packages comprises:
a package substrate having a top surface and a bottom surface opposite to each other;
a plurality of semiconductor chips provided on the top surface of the package substrate, the plurality of semiconductor chips being arranged so as to be adjacent to each other in a second direction crossing the first direction; and
a plurality of through electrodes electrically connecting the plurality of semiconductor chips to the package substrate and penetrating at least a portion of the plurality of semiconductor chips, respectively; and

wherein:
the first and second directions are parallel to the top surface of the module substrate; and
the electric connection element is not present between a package substrate of any of the semiconductor packages and the module substrate along a direction perpendicular to the top surface of the module substrate.

10. The semiconductor module of claim 9 , further comprising a connection region provided between the module substrate and the package substrate to electrically connect the semiconductor packages to the module substrate, the connection region comprising, for each semiconductor package:
a first region electrically connected between data signal terminals of the semiconductor chips and the module substrate; and
a second region electrically connected between command/address signal terminals of the semiconductor chips and the module substrate;
wherein the first region and the second region are arranged in the second direction on the bottom surface of the package substrate.

11. The semiconductor module of claim 10 , wherein the first region is closer to the electric connection element than the second region.

12. The semiconductor module of claim 11 , wherein for each semiconductor package, the semiconductor chips comprise:
a first semiconductor chip adjacent to the electric connection element; and
a second semiconductor chip further from the electric connection element than the first semiconductor chip;
wherein the first region comprises:
a first data connection region electrically connected to data signal terminals of the first semiconductor chip; and
a second data connection region electrically connected to data signal terminals of the second semiconductor chip.

13. The semiconductor module of claim 12 , wherein:
the second region comprises a common connection region electrically connected to the command/address signal terminals of the first and second semiconductor chips, and
the first and second semiconductor chips are electrically connected to the common connection region to share a command/address signal transmitted through the common connection region.

14. The semiconductor module of claim 12 , wherein the first and second data connection regions are arranged in the first direction on the bottom surface of the package substrate.

15. The semiconductor module of claim 12 , wherein a length of a transmission path of a data signal to be transmitted between the first data connection region and the electric connection element is equal to a length of a transmission path of a data signal to be transmitted between the second data connection region and the electric connection element.

16. A semiconductor module, comprising a plurality of semiconductor packages provided on a module substrate with an electric connection element, wherein the semiconductor p

Assignees

• Kim Kyoungsoo
• Kang Sunwon
• Samsung Electronics Co Ltd

Inventors

• Kim Kyoungsoo
• Kang Sunwon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/721

  of bump connectors · CPC title