Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates

Patent metadata

Field	Value
Publication number	US-10522452-B2
Application number	US-201113276143-A
Country	US
Kind code	B2
Filing date	Oct 18, 2011
Priority date	Oct 18, 2011
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

First claim

What is claimed is:

1. A method of packaging a semiconductor device, the method comprising:
providing a workpiece, the workpiece including a plurality of packaging substrates;
removing a top portion of the workpiece between adjacent ones of the plurality of packaging substrates to form a top trench in the workpiece and removing a bottom portion of the workpiece between the adjacent ones of the plurality of packaging substrates to form a bottom trench in the workpiece, wherein the top trench and the bottom trench are vertically aligned, and wherein at least a portion of the workpiece is interposed between a bottom of the top trench and a bottom of the bottom trench;
after forming the top trench and the bottom trench in the workpiece, attaching a die to each of the plurality of packaging substrates; and
separating the plurality of packaging substrates from one another, wherein after separating the plurality of packaging substrates from one another the workpiece remains continuous and unbroken from at least a first side of the die to a second opposite side of the die.

2. The method according to claim 1 , wherein the die includes a plurality of bumps disposed on a surface thereof, and the method further comprises attaching the plurality of bumps on the surface of the die to each of the plurality of packaging substrates.

3. The method according to claim 2 , wherein providing the die comprises providing a die wherein the plurality of bumps disposed thereon comprises solder.

4. The method according to claim 3 , further comprising performing a solder process, a solder reflow process, or a thermal compression bonding process.

5. The method according to claim 3 , wherein removing the top portion of the workpiece comprises removing about 20 μm or greater of depth of the workpiece.

6. The method according to claim 1 , further comprising forming an under-fill material under the dies, and forming a molding compound over the dies and the under-fill material.

7. The method of claim 1 , wherein the top trench is formed by removing a solder mask and at least a portion of a dielectric material that are both formed on a same side of the workpiece.

8. A method of packaging a semiconductor device, the method comprising:
providing a workpiece, the workpiece comprising a plurality of packaging substrates;
forming a dielectric material on the workpiece, proximate to a first surface of the workpiece and distal from a second surface of the workpiece, the second surface being opposite the first surface;
forming a plurality of bond pads over the dielectric material, proximate to the first surface of the workpiece and distal from the second surface of the workpiece;
forming a solder mask over the plurality of bond pads and the dielectric material and proximate to the first surface of the workpiece and distal from the second surface of the workpiece;
forming a plurality of contact pads on the workpiece, proximate to the second surface of the workpiece and distal from the first surface of the workpiece;
after forming the plurality of contact pads, removing at least the solder mask between adjacent ones of the plurality of packaging substrates to form a recess, each of the plurality of contact pads being closer to the second surface of the workpiece than a bottom surface of the recess;
after removing at least the solder mask between adjacent ones of the plurality of packaging substrates, attaching a die to each of the plurality of packaging substrates, the die including a plurality of bumps disposed thereon; and
electrically coupling the plurality of bumps of the die to the plurality of bond pads, the plurality of bumps of the die extending into the solder mask and being in physical contact with top surfaces of the plurality of bond pads.

9. The method according to claim 8 , further comprising removing at least a portion of the dielectric material between adjacent ones of the plurality of packaging substrates.

10. The method according to claim 8 , wherein removing at least the solder mask comprises removing at least the solder mask in a separation region of the workpiece.

11. The method according to claim 8 , wherein providing the workpiece comprises providing a workpiece wherein the plurality of packaging substrates comprises a plurality of flip-chip ball grid array (FC-BGA) packages, flip-chip chip scale packages (FC-CSP), land grid array (LGA) packages, or bond-on-trace (BOT) packages.

12. The method according to claim 8 , wherein the plurality of packaging substrates includes a plurality of conductive layers, the plurality of conductive layers coupling the plurality of bond pads to the plurality of contact pads.

13. The method according to claim 8 , wherein removing at least the solder mask comprises using a laser, a die saw, or lithography.

14. The method according to claim 8 , wherein the solder mask is formed in physical contact with the dielectric material.

15. A method of packaging a semiconductor device, the method comprising:
providing a workpiece comprising a plurality of packaging substrates;
forming a dielectric material on a first surface of the workpiece;
forming a solder mask on the dielectric material, wherein the workpiece is not between the solder mask and the dielectric material;
forming a plurality of contact pads on a second surface of the workpiece, the second surface of the workpiece being opposite the first surface of the workpiece;
removing the solder mask and at least a portion of the dielectric material between adjacent ones of the plurality of packaging substrates to form a trench on separation regions between adjacent ones of the plurality of packaging substrates, each of the plurality of contact pads being closer to the second surface of the workpiece than a bottom of the trench;
attaching a die to each of the plurality of packaging substrates, each die including a plurality of bumps disposed thereon, the plurality of bumps including solder, the plurality of bumps extending through the solder mask;
reflowing the solder of the plurality of bumps of the dies using a solder reflow process; and
singulating the plurality of packaging substrates.

16. The method according to claim 15 , wherein attaching the die comprises attaching an integrated circuit die wherein the plurality of bumps disposed thereon comprise a plurality of micro-bumps.

17. The method according to claim 15 , wherein removing the solder mask and the at least a portion of the dielectric material between adjacent ones of the plurality of packaging substrates on separation regions between adjacent ones of the plurality of packaging substrates comprises removing the solder mask and the at least a portion of the dielectric material in an x-axis direction, a y-axis direction, or both an x-axis direction and a y-axis direction in a top view of the workpiece.

18. The method according to claim 15 , wherein forming the dielectric material comprises forming a dielectric material having a thickness of about 100 μm or less.

19. The method according to claim 15 , wherein forming the solder mask comprises forming a solder mask having a thickness of about 10 to 30 μm.

20. The method according to claim 15 , wherein removing at least the portion of the dielectric material comprises removing all of the dielectric material from between the plurality of packaging substrates.

21. The method according to claim 15 , wherein removing the solder mask and the at least the portion of the dielectric material between adjacent ones of the plurality of

Assignees

• Huang Kuei Wei
• Lin Wei Hung
• Lin Chih Wei
• Lin Chun Cheng
• Chen Meng Tse
• Cheng Ming Da
• Liu Ching Shi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Kuei-Wei
• Lin Wei-Hung
• Lin Chih-Wei
• Lin Chun-Cheng
• Chen Meng-Tse
• Cheng Ming-Da
• Liu Ching-Shi

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title