Traffic shaping in networking system-on-chip verification

Patent metadata

Field	Value
Publication number	US-10521544-B2
Application number	US-201715792101-A
Country	US
Kind code	B2
Filing date	Oct 24, 2017
Priority date	Oct 25, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device. The ingress transaction-level messages and the traffic-shaping information are then sent to a reconfigurable hardware modeling device. The ingress transaction-level messages are converted to ingress signal-level messages by a hardware model of interface circuitry implemented in the reconfigurable hardware modeling device. Based on the traffic-shaping information, the ingress signal-level messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device.

First claim

What is claimed is:

1. A method, comprising:
associating traffic-shaping information with ingress transaction-level messages by a traffic generation device;
sending the ingress transaction-level messages and the traffic-shaping information to a reconfigurable hardware modeling device;
converting the ingress transaction-level messages to ingress signal-level messages by a hardware model of interface circuitry implemented in the reconfigurable hardware modeling device; and
delivering, based on the traffic-shaping information, the ingress signal-level messages to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device.

2. The method recited in claim 1 , wherein the traffic-shaping information comprises inter-frame gap data, inter-burst gap data, or both.

3. The method recited in claim 2 , wherein the inter-frame gap information is on a per-frame basis.

4. The method recited in claim 1 , wherein the associating comprises:
inserting the traffic-shaping information in the ingress transaction-level messages.

5. The method recited in claim 4 , wherein the traffic-shaping information is contained in a metadata field of the ingress transaction-level messages.

6. The method recited in claim 4 , wherein the traffic-shaping information is contained in a data field of the ingress transaction-level messages.

7. The method recited in claim 1 , wherein the associating comprises:
inserting the traffic-shaping information in traffic-shaping messages, the traffic-shaping message being different from the ingress transaction-level message.

8. The method recited in claim 1 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.

9. The method recited in claim 1 , wherein the traffic generation device is implemented at least in part by a network traffic tool, wherein the network traffic tool is implemented by a virtual machine running on a computer.

10. The method recited in claim 1 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.

11. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to generate bitstreams for programming a reconfigurable hardware modeling device to implement circuitry hardware models, the circuitry hardware models comprising:
a hardware model of a circuit design, and
a hardware model of interface circuitry that converts ingress transaction-level messages to ingress signal-level messages and delivers, based on traffic-shaping information, the ingress signal-level messages to the hardware model of the circuit design, wherein the ingress transaction-level messages and the traffic-shaping information are generated and sent by a traffic generation device.

12. The one or more non-transitory computer-readable media recited in claim 11 , wherein the traffic-shaping information comprises interpacket gap information, interburst gap information, or both.

13. The one or more non-transitory computer-readable media recited in claim 12 , wherein the interpacket gap information is on a per-packet basis.

14. The one or more non-transitory computer-readable media recited in claim 11 , wherein the traffic-shaping information is inserted in the ingress transaction-level messages.

15. The one or more non-transitory computer-readable media recited in claim 14 , wherein the traffic-shaping information is contained in a metadata field of the ingress transaction-level messages.

16. The one or more non-transitory computer-readable media recited in claim 14 , wherein the traffic-shaping information is contained in a data field of the ingress transaction-level messages.

17. The one or more non-transitory computer-readable media recited in claim 11 , wherein the traffic-shaping information is contained in traffic-shaping messages, the traffic-shaping message packets being different from the ingress transaction-level message packets.

18. The one or more non-transitory computer-readable media recited in claim 11 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.

19. The one or more non-transitory computer-readable media recited in claim 11 , wherein the traffic generation device is implemented at least in part by a network traffic tool, wherein the network traffic tool is implemented by a virtual machine running on a computer.

20. The one or more non-transitory computer-readable media recited in claim 11 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.

21. A reconfigurable hardware modeling device programmed to implement circuitry hardware models, the circuitry hardware models comprising:
a hardware model of a circuit design, and
a hardware model of interface circuitry that converts ingress transaction-level messages to ingress signal-level messages and delivers, based on traffic shaping information, the ingress signal-level messages to the hardware model of the circuit design, wherein the ingress transaction-level messages and the traffic shaping information are generated and sent by a traffic generation device.

22. The reconfigurable hardware modeling device recited in claim 21 , wherein the traffic shaping information comprises interpacket gap information, interburst gap information, or both.

23. The reconfigurable hardware modeling device recited in claim 22 , wherein the interpacket gap information is on a per-packet basis.

24. The reconfigurable hardware modeling device recited in claim 21 , wherein the traffic-shaping information is inserted in the ingress transaction-level messages.

25. The reconfigurable hardware modeling device recited in claim 24 , wherein the traffic-shaping information is contained in a metadata field of the ingress transaction-level messages.

26. The reconfigurable hardware modeling device recited in claim 24 , wherein the traffic-shaping information is contained in a data field of the ingress transaction-level messages.

27. The reconfigurable hardware modeling device recited in claim 21 , wherein the traffic-shaping information is contained in traffic-shaping messages, the traffic-shaping messages being different from the ingress transaction-level messages.

28. The reconfigurable hardware modeling device recited in claim 21 is a hardware-based emulator or an FPGA-based prototyping device.

29. The reconfigurable hardware modeling device recited in claim 21 , wherein the traffic generation device is implemented at least in part by a network traffic tool, wherein the network traffic tool is implemented by a virtual machine running on a computer.

30. The reconfigurable hardware modeling device recited in claim 21 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.

Assignees

• Mentor Graphics Corp

Inventors

• Suresh Krishnamurthy
• Garg Deepak Kumar
• Jayaswal Sudhanshu
• Khaitan Saurabh
• Gupta Sanjay
• Stickley John R
• Vreeland Iii Russell Elias
• Squiers Ronald James

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F11/2289

  by configuration test · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title