Data-dependent delay circuits

Patent metadata

Field	Value
Publication number	US-10521530-B2
Application number	US-201715636902-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Jul 28, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes:
obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

First claim

What is claimed is:

1. A method of designing a logic circuit with data-dependent delays, wherein said logic circuit comprises a plurality of logic paths from logic inputs to at least one logic output, said method comprising:
using an electronic design automation system:
obtaining an initial circuit design;
specifying respective delays for a plurality of logic paths in said initial circuit design such that at least some of said outputs switch at different times within a clock cycle for different combinations of logic input levels; and
forming a second circuit design having said specified respective delays along said respective logic paths by adding delay elements to said initial circuit design based on said specified respective delays,
wherein for at least one of said logic paths said method further comprises:
calculating a respective initial delay for said at least one logic path by analyzing said initial circuit design; and
based on said initial delay, calculating a number of delay elements required for insertion into said at least one logic path to obtain said specified respective delay.

2. A method according to claim 1 , further comprising:
analyzing a power utilization spread of said second circuit design;
calculating an attainable power utilization spread of said initial circuit design; and
when said power utilization spread of said second circuit design is less than said attainable power utilization spread, changing at least one of said delays to form a third circuit design having a greater power utilization spread.

3. A method according to claim 1 , wherein said forming a second circuit design comprises:
selecting locations in logic paths of said initial circuit design for embedding delay elements to obtain said specified respective delays along said logic paths; and
embedding said delay elements into said selected locations.

4. A method according to claim 1 , wherein at least one of said delay elements comprises:
a buffer;
a combination of buffers;
a logic gate;
a combination of logic gates;
a wire;
a resistive element;
a capacitive element; and
a connection between logic gates.

5. A method according to claim 1 , wherein said adding delay elements comprises at least one of:
inserting a resistive element into said initial design;
inserting a capacitive element into said initial design;
adjusting cell sizing;
adjusting circuit layout; and
tuning driving strength.

6. A method according to claim 1 , wherein said respective delays create intra-cycle delays within a single output for different combinations of logic input levels.

7. A method according to claim 1 , wherein said respective delays create intra-cycle delays amongst a plurality of said outputs for different combinations of logic input levels.

8. A method according to claim 1 , wherein said respective delays create, for different combinations of logic input levels, intra-cycle delays within at least one single output and amongst a plurality of said outputs.

9. A method according to claim 1 , further comprising adjusting said second circuit design to reduce a maximal number of delay elements respectively added to said logic paths.

10. A method according to claim 1 , further comprising adjusting said second circuit design to reduce a respective difference between a maximal and minimal number of delay elements assigned to logic paths within each logic cone from said logic inputs to said logic outputs, and to reduce a respective difference between a maximal and minimal number of delay elements assigned to logic paths in which switching activity occurs simultaneously at different outputs.

11. A method according to claim 1 , wherein said specifying comprises:
partitioning said logic paths into groups, at least one of said groups comprising a plurality of logic paths in which switching activity occurs simultaneously at different outputs; and
for at least one of said groups, assigning different respective delays to logic paths within said group.

12. A method according to claim 1 , wherein said specifying comprises:
identifying sets of inputs with correlated switching times for a plurality of outputs; and
for at least one of said sets of inputs, assigning different respective delays to logic paths from inputs in said set to said outputs with correlated switching.

13. A method according to claim 1 , wherein said specifying comprises assigning a respective common delay to all logic paths to a single output, wherein said respective common delays are different for at least some of said outputs.

14. A method according to claim 1 , wherein said specifying comprises assigning different respective delays to at least some logic paths to a single output.

15. A method according to claim 1 , wherein for at least some of said logic paths, a number of delay elements added to said logic path is randomly selected from a specified range.

16. A method according to claim 1 , wherein said logic circuit comprises a logic cone comprising a plurality of logic paths from said inputs to a single output, and said specifying comprises:
forming a delay vector, a length of said delay vector equaling at least a number of said logic paths in said logic cone, each element of said delay vector specifying a number of delay elements;
forming a set of permutations of said delay vector;
randomly selecting one of said permutations;
for each of said logic paths forming said logic cone, adding a number of delay elements given by a respective element of said selected permutation.

17. A method according to claim 1 , wherein said specifying comprises:
partitioning said logic paths into groups, at least one of said groups comprising a plurality of logic paths in which switching activity will occur simultaneously at different outputs;
generating a mates matrix, each row of said matrix corresponding to a respective one of said groups, each column of said matrix corresponding to a respective one of said outputs, wherein each cell of said matrix specifies a path from said respective group to said respective output;
for each row of said mates matrix, assigning a different respective number of delay elements to each path in said row;
for each column of said mates matrix, assigning a different respective number of delay elements to each path in said column; and
calculating a respective number of delay elements to add to each of said logic paths to conform to said mates matrix.

18. A method according to claim 10 , further comprising reducing a difference between a maximal and a minimal number of delay elements assigned to each of said rows and a difference between a maximal and a minimal number of delay elements assigned to each of said columns to the smallest possible numbers.

19. A method according to claim 10 , further comprising reducing a maximal number of delay elements assigned to said cells to a smallest possible number.

20. A method according to claim 1 , further comprising adjusting said second circuit design to reduce resource costs for embedding said delay elements in said logic paths to obtain said specified respective delays.

21. A method according to claim 20 , wherein said resource costs comprise at least one of:
circuit area;
circuit power consumption; and
a total number of delay elements added to said logic circuit.

22. A method according to claim 1 , wherein said logic circuit comprises a plurality of logic cones from said logic inputs to said logic outputs and said specifying is performed i

Assignees

• Univ Bar Ilan

Inventors

• Levi Itamar
• Keren Osnat
• Fish Alexander

Classifications

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title