Method of scheduling system-on-chip including real-time shared interface

Patent metadata

Field	Value
Publication number	US-10521382-B2
Application number	US-201916421269-A
Country	US
Kind code	B2
Filing date	May 23, 2019
Priority date	Aug 26, 2015
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method of scheduling a system-on-chip (SoC) by a scheduler, located between a plurality of masters and a slave, includes receiving a plurality of access requests from the plurality of masters, setting the plurality of access requests in a plurality of registers, and scheduling the plurality of access requests based on the plurality of access requests.

First claim

What is claimed is:

1. An apparatus comprising:
a first master configured to transmit a first access request;
a second master configured to transmit a second access request;
a slave shared by the first master and the second master, and configured to transmit an interrupt;
a bus;
an interface shared in real time by the first master and the second master; and
a scheduler circuit configured to receives the first access request and the second access request via the bus, configured to transmit either the first access request or the second access request to the slave via the interface, to receive the interrupt from the slave via the interface, and configured to transmit the interrupt to either the first master or the second master via the bus,
wherein the scheduler circuit includes:
a first register configured to store the first access request;
a second register configured to store the second access request;
a controller configured to set a first time limit value of the first master and a second time limit value of the second master based on a first time boundary of the first master and a second time boundary of the second master, and configured to select either the first access request or the second access request based on a minimum time limit value;
a first counter configured to store the first time limit value;
a second counter configured to store the second time limit value; and
a comparator configured to compare the first time limit value and the second time limit value, and configured to output to the controller the minimum time limit value among the first time limit value and the second time limit value.

2. The apparatus of claim 1 , wherein the apparatus includes a system-on-chip (SoC).

3. The apparatus of claim 1 , wherein the scheduler circuit schedules the first access request and the second access request.

4. The apparatus of claim 1 , wherein the scheduler circuit determines whether a precondition is satisfied based on the first time limit value and the second time limit value.

5. The apparatus of claim 4 , wherein the precondition prevents an operation time period of the first master and an operation time of the second master from overlapping when the first master and the second master communicate with the slave a plurality of times in a predetermined cycle.

6. The apparatus of claim 4 , wherein when the precondition is not satisfied, the scheduler circuit transmits a schedule uncontrollability message to the first master and the second master.

7. The apparatus of claim 4 , wherein when the precondition is satisfied, the controller transmits the first time limit value to the first counter and transmits the second time limit value to the second counter.

8. The apparatus of claim 1 , wherein the minimum time limit value is greater than zero.

9. An apparatus comprising:
a first master configured to transmit a first access request;
a second master configured to transmit a second access request;
a slave shared by the first master and the second master; and
a scheduler circuit configured to receives the first access request and the second access request, configured to transmit either the first access request or the second access request to the slave, configured to set a first time limit value of the first master and a second time limit value of the second master, and configured to select either the first access request or the second access request based on the first time limit value and the second time limit value.

10. The apparatus of claim 9 , further comprising:
a bus through which the first access request and the second access request are transmitted; and
an interface shared in real time by the first master and the second master.

11. The apparatus of claim 9 , wherein the scheduler circuit receives an interrupt from the slave, and transmits the interrupt to either the first master or the second master.

12. The apparatus of claim 9 , wherein the scheduler circuit includes
a first register configured to store the first access request;
a second register configured to store the second access request;
a controller configured to set the first time limit value and the second time limit value based on a first time boundary of the first master and a second time boundary of the second master, and configured to select either the first access request or the second access request based on a minimum time limit value;
a first counter configured to store the first time limit value;
a second counter configured to store the second time limit value; and
a comparator configured to compare the first time limit value and the second time limit value, and configured to output to the controller the minimum time limit value among the first time limit value and the second time limit value, the minimum time limit value being greater than zero.

13. The apparatus of claim 12 , wherein the scheduler circuit determines whether a precondition is satisfied based on the first time limit value and the second time limit value.

14. The apparatus of claim 13 , wherein when the precondition is not satisfied, the scheduler circuit transmits a schedule uncontrollability message to the first master and the second master, and
when the precondition is satisfied, the controller transmits the first time limit value to the first counter and transmits the second time limit value to the second counter.

15. The apparatus of claim 12 , wherein the controller outputs a control signal to the first counter and the second counter, and changes the first time limit value stored in the first counter and the second time limit value stored in the second counter.

16. An apparatus comprising:
a first master configured to transmit a first access request;
a second master configured to transmit a second access request;
a slave shared by the first master and the second master; and
a scheduler circuit configured to receives the first access request and the second access request, and configured to transmit either the first access request or the second access request to the slave,
wherein the scheduler circuit includes:
a first register configured to store the first access request;
a second register configured to store the second access request;
a controller configured to set a first time limit value of the first master and a second time limit value of the second master, and configured to select either the first access request or the second access request based on a minimum time limit value;
a first counter configured to store the first time limit value;
a second counter configured to store the second time limit value; and
a comparator configured to compare the first time limit value and the second time limit value, and configured to output to the controller the minimum time limit value among the first time limit value and the second time limit value.

17. The apparatus of claim 16 , wherein the slave transmits an interrupt to the scheduler circuit, and
the scheduler circuit transmits the interrupt to either the first master or the second master via the bus.

18. The apparatus of claim 16 , wherein the scheduler circuit determines whether a precondition is satisfied based on the first time limit value and the second time limit value, and
when the precondition is not satisfied, the scheduler circuit transmits a schedule uncontrollability message to the first master and the second master.

19. The apparatus of claim 16 , wherein the scheduler circuit performs scheduling based on an operation of the slave.

20. The apparatus of cl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Dong Sik

Classifications

• G06F13/368 Primary

  with decentralised access control · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title